powerpc/mpc8308rdb: support for MPC8308RDB board from Freescale
This patch adds support for MPC8308RDB development board from
Freescale.
Supported devices:
DUART
Dual Ethernet
NOR and NAND flashes
I2C
USB in peripheral mode
PCIE support is broken by the commit 3da34aa ("powerpc/fsl: Support
unique MSI addresses per PCIe Root Complex"). Works after revert.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Ilya Yanok
Kumar Gala
parent
e3b5e0d552
commit
ba4d1275d1
303
arch/powerpc/boot/dts/mpc8308rdb.dts
Normal file
303
arch/powerpc/boot/dts/mpc8308rdb.dts
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@ -0,0 +1,303 @@
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/*
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* MPC8308RDB Device Tree Source
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*
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* Copyright 2009 Freescale Semiconductor Inc.
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* Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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compatible = "fsl,mpc8308rdb";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8308@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <16384>;
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i-cache-size = <16384>;
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timebase-frequency = <0>; // from bootloader
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bus-frequency = <0>; // from bootloader
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clock-frequency = <0>; // from bootloader
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x08000000>; // 128MB at 0
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};
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localbus@e0005000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
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reg = <0xe0005000 0x1000>;
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interrupts = <77 0x8>;
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interrupt-parent = <&ipic>;
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// CS0 and CS1 are swapped when
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// booting from nand, but the
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// addresses are the same.
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ranges = <0x0 0x0 0xfe000000 0x00800000
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0x1 0x0 0xe0600000 0x00002000
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0x2 0x0 0xf0000000 0x00020000
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0x3 0x0 0xfa000000 0x00008000>;
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flash@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x800000>;
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bank-width = <2>;
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device-width = <1>;
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u-boot@0 {
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reg = <0x0 0x60000>;
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read-only;
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};
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env@60000 {
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reg = <0x60000 0x10000>;
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};
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env1@70000 {
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reg = <0x70000 0x10000>;
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};
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kernel@80000 {
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reg = <0x80000 0x200000>;
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};
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dtb@280000 {
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reg = <0x280000 0x10000>;
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};
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ramdisk@290000 {
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reg = <0x290000 0x570000>;
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};
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};
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nand@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8315-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <0x1 0x0 0x2000>;
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jffs2@0 {
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reg = <0x0 0x2000000>;
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};
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};
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};
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immr@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,mpc8315-immr", "simple-bus";
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ranges = <0 0xe0000000 0x00100000>;
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reg = <0xe0000000 0x00000200>;
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bus-frequency = <0>;
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <14 0x8>;
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interrupt-parent = <&ipic>;
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dfsrr;
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rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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};
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usb@23000 {
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compatible = "fsl-usb2-dr";
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reg = <0x23000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&ipic>;
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interrupts = <38 0x8>;
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dr_mode = "peripheral";
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phy_type = "ulpi";
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};
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enet0: ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x24000 0x1000>;
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <32 0x8 33 0x8 34 0x8>;
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interrupt-parent = <&ipic>;
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tbi-handle = < &tbi0 >;
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phy-handle = < &phy2 >;
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fsl,magic-packet;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x520 0x20>;
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phy2: ethernet-phy@2 {
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interrupt-parent = <&ipic>;
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interrupts = <17 0x8>;
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reg = <0x2>;
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device_type = "ethernet-phy";
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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enet1: ethernet@25000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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ranges = <0x0 0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <35 0x8 36 0x8 37 0x8>;
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interrupt-parent = <&ipic>;
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tbi-handle = < &tbi1 >;
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/* Vitesse 7385 isn't on the MDIO bus */
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fixed-link = <1 1 1000 0 0>;
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fsl,magic-packet;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <133333333>;
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interrupts = <9 0x8>;
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interrupt-parent = <&ipic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <133333333>;
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interrupts = <10 0x8>;
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interrupt-parent = <&ipic>;
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};
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gpio@c00 {
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#gpio-cells = <2>;
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device_type = "gpio";
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compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
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reg = <0xc00 0x18>;
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interrupts = <74 0x8>;
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interrupt-parent = <&ipic>;
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gpio-controller;
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};
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/* IPIC
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* interrupts cell = <intr #, sense>
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* sense values match linux IORESOURCE_IRQ_* defines:
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* sense == 8: Level, low assertion
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* sense == 2: Edge, high-to-low change
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*/
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ipic: interrupt-controller@700 {
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compatible = "fsl,ipic";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x700 0x100>;
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device_type = "ipic";
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};
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ipic-msi@7c0 {
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compatible = "fsl,ipic-msi";
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reg = <0x7c0 0x40>;
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msi-available-ranges = <0x0 0x100>;
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interrupts = < 0x43 0x8
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0x4 0x8
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0x51 0x8
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0x52 0x8
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0x56 0x8
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0x57 0x8
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0x58 0x8
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0x59 0x8 >;
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interrupt-parent = < &ipic >;
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};
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};
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pci0: pcie@e0009000 {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
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reg = <0xe0009000 0x00001000
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0xb0000000 0x01000000>;
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ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
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0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
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bus-range = <0 0>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <0 0 0 1 &ipic 1 8
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0 0 0 2 &ipic 1 8
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0 0 0 3 &ipic 1 8
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0 0 0 4 &ipic 1 8>;
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interrupts = <0x1 0x8>;
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interrupt-parent = <&ipic>;
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clock-frequency = <0>;
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pcie@0 {
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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reg = <0 0 0 0 0>;
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ranges = <0x02000000 0 0xa0000000
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0x02000000 0 0xa0000000
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0 0x10000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00800000>;
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};
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};
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};
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@ -9,6 +9,14 @@ menuconfig PPC_83xx
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if PPC_83xx
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config MPC830x_RDB
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bool "Freescale MPC830x RDB"
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select DEFAULT_UIMAGE
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select PPC_MPC831x
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select FSL_GTM
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help
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This option enables support for the MPC8308 RDB board.
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config MPC831x_RDB
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bool "Freescale MPC831x RDB"
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select DEFAULT_UIMAGE
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@ -4,6 +4,7 @@
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obj-y := misc.o usb.o
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obj-$(CONFIG_SUSPEND) += suspend.o suspend-asm.o
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obj-$(CONFIG_MCU_MPC8349EMITX) += mcu_mpc8349emitx.o
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obj-$(CONFIG_MPC830x_RDB) += mpc830x_rdb.o
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obj-$(CONFIG_MPC831x_RDB) += mpc831x_rdb.o
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obj-$(CONFIG_MPC832x_RDB) += mpc832x_rdb.o
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obj-$(CONFIG_MPC834x_MDS) += mpc834x_mds.o
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94
arch/powerpc/platforms/83xx/mpc830x_rdb.c
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94
arch/powerpc/platforms/83xx/mpc830x_rdb.c
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@ -0,0 +1,94 @@
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/*
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* arch/powerpc/platforms/83xx/mpc830x_rdb.c
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*
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* Description: MPC830x RDB board specific routines.
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* This file is based on mpc831x_rdb.c
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*
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* Copyright (C) Freescale Semiconductor, Inc. 2009. All rights reserved.
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* Copyright (C) 2010. Ilya Yanok, Emcraft Systems, yanok@emcraft.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/pci.h>
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#include <linux/of_platform.h>
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#include <asm/time.h>
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#include <asm/ipic.h>
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#include <asm/udbg.h>
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#include <sysdev/fsl_pci.h>
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#include <sysdev/fsl_soc.h>
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#include "mpc83xx.h"
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/*
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* Setup the architecture
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*/
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static void __init mpc830x_rdb_setup_arch(void)
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{
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#ifdef CONFIG_PCI
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struct device_node *np;
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#endif
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if (ppc_md.progress)
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ppc_md.progress("mpc830x_rdb_setup_arch()", 0);
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#ifdef CONFIG_PCI
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for_each_compatible_node(np, "pci", "fsl,mpc8308-pcie")
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mpc83xx_add_bridge(np);
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#endif
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mpc831x_usb_cfg();
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}
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static void __init mpc830x_rdb_init_IRQ(void)
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{
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struct device_node *np;
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np = of_find_node_by_type(NULL, "ipic");
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if (!np)
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return;
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ipic_init(np, 0);
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/* Initialize the default interrupt mapping priorities,
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* in case the boot rom changed something on us.
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*/
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ipic_set_default_priority();
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}
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/*
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* Called very early, MMU is off, device-tree isn't unflattened
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*/
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static int __init mpc830x_rdb_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "MPC8308RDB") ||
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of_flat_dt_is_compatible(root, "fsl,mpc8308rdb");
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}
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static struct of_device_id __initdata of_bus_ids[] = {
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{ .compatible = "simple-bus" },
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{ .compatible = "gianfar" },
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{},
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};
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static int __init declare_of_platform_devices(void)
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{
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of_platform_bus_probe(NULL, of_bus_ids, NULL);
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return 0;
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}
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machine_device_initcall(mpc830x_rdb, declare_of_platform_devices);
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define_machine(mpc830x_rdb) {
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.name = "MPC830x RDB",
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.probe = mpc830x_rdb_probe,
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.setup_arch = mpc830x_rdb_setup_arch,
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.init_IRQ = mpc830x_rdb_init_IRQ,
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.get_irq = ipic_get_irq,
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.restart = mpc83xx_restart,
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.time_init = mpc83xx_time_init,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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