clk: imx: correct AV PLL rate formula
The audio/video PLL's rate calculation is as below in RM: Fref * (DIV_SELECT + NUM / DENOM), in origin clk-pllv3's code, below code is used: (parent_rate * div) + ((parent_rate / mfd) * mfn as it does NOT consider the float data using div, so below formula should be used as a decent method: (parent_rate * div) + ((parent_rate * mfn) / mfd) and we also need to consider parent_rate * mfd may overflow a 32 bit value, 64 bit value should be used. After updating this formula, the dram PLL's rate is 1066MHz, which is correct, while the old formula gets 1056MHz. [Aisheng: fix clk_pllv3_av_round_rate too] Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -218,8 +218,12 @@ static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
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u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
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u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
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u32 div = readl_relaxed(pll->base) & pll->div_mask;
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u64 temp64 = (u64)parent_rate;
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return (parent_rate * div) + ((parent_rate / mfd) * mfn);
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temp64 *= mfn;
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do_div(temp64, mfd);
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return (parent_rate * div) + (u32)temp64;
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}
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static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
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@ -243,7 +247,7 @@ static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
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do_div(temp64, parent_rate);
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mfn = temp64;
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return parent_rate * div + parent_rate / mfd * mfn;
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return parent_rate * div + parent_rate * mfn / mfd;
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}
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static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
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