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Allwinner DT changes for 4.19 

There's a number of additions for the ARMv7 SoCs for this merge window, and
 especially:
 
   - Addition of the system controller for a number of SoCs, as part of the
     VPU effort
   - Addition of the R40 HDMI support
   - Addition of the Mali GPU node for the A10
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Merge tag 'sunxi-dt-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt

Allwinner DT changes for 4.19

There's a number of additions for the ARMv7 SoCs for this merge window, and
especially:

  - Addition of the system controller for a number of SoCs, as part of the
    VPU effort
  - Addition of the R40 HDMI support
  - Addition of the Mali GPU node for the A10

* tag 'sunxi-dt-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits)
  ARM: dts: sun4i: Add GPU node
  ARM: dts: sun5i: Fix the SRAM A3-A4 declaration
  ARM: dts: sun8i: r40: Remove unused address-cells/size-cells of dwmac-sun8i
  ARM: dts: sun8i: a83t: Remove unused address-cells/size-cells of dwmac-sun8i
  dt-bindings: net: dwmac-sun8i: Remove unused address-cells/size-cells
  ARM: dts: sun8i: h3: Add SRAM controller node and C1 SRAM region
  ARM: dts: sun8i: a23-a33: Add SRAM controller node and C1 SRAM region
  ARM: dts: sun7i: Add support for the C1 SRAM region with the SRAM controller
  ARM: dts: sun5i: Add support for the C1 SRAM region with the SRAM controller
  ARM: dts: sun7i: Use most-qualified system control compatibles
  ARM: dts: sun5i: Use most-qualified system control compatibles
  ARM: dts: sun4i: Switch to new system control compatible string
  ARM: dts: sun8i: r40: Disable TCONs by default.
  ARM: dts: sun8i: r40: Add missing TCON-TOP - TCON connections
  ARM: dts: sun8i: r40: Remove fallback compatible for TCON TV
  ARM: dts: sun8i: r40: Add mixer ids to TCON TOP
  ARM: dts: sun8i: r40: Remove fallback display engine compatible
  ARM: dts: sun8i: a83t: Add CPU regulator supplies for A83T boards
  ARM: dts: sun8i: r40: Enable HDMI output on BananaPi M2 Ultra
  ARM: dts: sun8i: r40: Add HDMI pipeline
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
hifive-unleashed-5.1
Olof Johansson 2018-07-25 23:55:23 -07:00
parent 9604ff923c c0476a31fb
commit ba8e2b94d9
14 changed files with 534 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/devicetree/bindings/net/dwmac-sun8i.txt
View File

@ -19,8 +19,6 @@ Required properties:
- reset-names: must be "stmmaceth"
- phy-mode: See ethernet.txt
- phy-handle: See ethernet.txt
- #address-cells: shall be 1
- #size-cells: shall be 0
- syscon: A phandle to the device containing the EMAC or GMAC clock register
Optional properties:
@ -86,8 +84,6 @@ emac: ethernet@1c0b000 {
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
@ -137,8 +133,6 @@ emac: ethernet@1c0b000 {
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
@ -191,8 +185,6 @@ emac: ethernet@1c0b000 {
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";

25
arch/arm/boot/dts/sun4i-a10.dtsi
View File

@ -190,8 +190,8 @@
#size-cells = <1>;
ranges;
sram-controller@1c00000 {
compatible = "allwinner,sun4i-a10-sram-controller";
system-control@1c00000 {
compatible = "allwinner,sun4i-a10-system-control";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
@ -1001,6 +1001,27 @@
status = "disabled";
};
mali: gpu@1c40000 {
compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
reg = <0x01c40000 0x10000>;
interrupts = <69>,
<70>,
<71>,
<72>,
<73>;
interrupt-names = "gp",
"gpmmu",
"pp0",
"ppmmu0",
"pmu";
clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
clock-names = "bus", "core";
resets = <&ccu RST_GPU>;
assigned-clocks = <&ccu CLK_GPU>;
assigned-clock-rates = <384000000>;
};
fe0: display-frontend@1e00000 {
compatible = "allwinner,sun4i-a10-display-frontend";
reg = <0x01e00000 0x20000>;

32
arch/arm/boot/dts/sun5i.dtsi
View File

@ -114,8 +114,8 @@
#size-cells = <1>;
ranges;
sram-controller@1c00000 {
compatible = "allwinner,sun4i-a10-sram-controller";
system-control@1c00000 {
compatible = "allwinner,sun5i-a13-system-control";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
@ -127,12 +127,13 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00000000 0xc000>;
};
emac_sram: sram-section@8000 {
compatible = "allwinner,sun4i-a10-sram-a3-a4";
reg = <0x8000 0x4000>;
status = "disabled";
emac_sram: sram-section@8000 {
compatible = "allwinner,sun5i-a13-sram-a3-a4",
"allwinner,sun4i-a10-sram-a3-a4";
reg = <0x8000 0x4000>;
status = "disabled";
};
};
sram_d: sram@10000 {
@ -143,11 +144,26 @@
ranges = <0 0x00010000 0x1000>;
otg_sram: sram-section@0 {
compatible = "allwinner,sun4i-a10-sram-d";
compatible = "allwinner,sun5i-a13-sram-d",
"allwinner,sun4i-a10-sram-d";
reg = <0x0000 0x1000>;
status = "disabled";
};
};
sram_c: sram@1d00000 {
compatible = "mmio-sram";
reg = <0x01d00000 0xd0000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x01d00000 0xd0000>;
ve_sram: sram-section@0 {
compatible = "allwinner,sun5i-a13-sram-c1",
"allwinner,sun4i-a10-sram-c1";
reg = <0x000000 0x80000>;
};
};
};
dma: dma-controller@1c02000 {

30
arch/arm/boot/dts/sun6i-a31.dtsi
View File

@ -119,18 +119,48 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
/* kHz uV */
1008000 1200000
864000 1200000
720000 1100000
480000 1000000
>;
#cooling-cells = <2>;
};
cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <2>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
/* kHz uV */
1008000 1200000
864000 1200000
720000 1100000
480000 1000000
>;
#cooling-cells = <2>;
};
cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <3>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
/* kHz uV */
1008000 1200000
864000 1200000
720000 1100000
480000 1000000
>;
#cooling-cells = <2>;
};
};

38
arch/arm/boot/dts/sun7i-a20.dtsi
View File

@ -122,6 +122,19 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
/* kHz uV */
960000 1400000
912000 1400000
864000 1300000
720000 1200000
528000 1100000
312000 1000000
144000 1000000
>;
#cooling-cells = <2>;
};
};
@ -239,8 +252,9 @@
#size-cells = <1>;
ranges;
sram-controller@1c00000 {
compatible = "allwinner,sun4i-a10-sram-controller";
system-control@1c00000 {
compatible = "allwinner,sun7i-a20-system-control",
"allwinner,sun4i-a10-system-control";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
@ -254,7 +268,8 @@
ranges = <0 0x00000000 0xc000>;
emac_sram: sram-section@8000 {
compatible = "allwinner,sun4i-a10-sram-a3-a4";
compatible = "allwinner,sun7i-a20-sram-a3-a4",
"allwinner,sun4i-a10-sram-a3-a4";
reg = <0x8000 0x4000>;
status = "disabled";
};
@ -268,11 +283,26 @@
ranges = <0 0x00010000 0x1000>;
otg_sram: sram-section@0 {
compatible = "allwinner,sun4i-a10-sram-d";
compatible = "allwinner,sun7i-a20-sram-d",
"allwinner,sun4i-a10-sram-d";
reg = <0x0000 0x1000>;
status = "disabled";
};
};
sram_c: sram@1d00000 {
compatible = "mmio-sram";
reg = <0x01d00000 0xd0000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x01d00000 0xd0000>;
ve_sram: sram-section@0 {
compatible = "allwinner,sun7i-a20-sram-c1",
"allwinner,sun4i-a10-sram-c1";
reg = <0x000000 0x80000>;
};
};
};
nmi_intc: interrupt-controller@1c00030 {

22
arch/arm/boot/dts/sun8i-a23-a33.dtsi
View File

@ -124,6 +124,28 @@
#size-cells = <1>;
ranges;
system-control@1c00000 {
compatible = "allwinner,sun8i-a23-system-control";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram_c: sram@1d00000 {
compatible = "mmio-sram";
reg = <0x01d00000 0x80000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x01d00000 0x80000>;
ve_sram: sram-section@0 {
compatible = "allwinner,sun8i-a23-sram-c1",
"allwinner,sun4i-a10-sram-c1";
reg = <0x000000 0x80000>;
};
};
};
dma: dma-controller@1c02000 {
compatible = "allwinner,sun8i-a23-dma";
reg = <0x01c02000 0x1000>;

9
arch/arm/boot/dts/sun8i-a33.dtsi
View File

@ -132,21 +132,30 @@
};
cpu@1 {
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
};
cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <2>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
};
cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <3>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
};
};

8
arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
View File

@ -79,6 +79,14 @@
};
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&cpu100 {
cpu-supply = <&reg_dcdc3>;
};
&ehci0 {
status = "okay";
};

8
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
View File

@ -107,6 +107,14 @@
};
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&cpu100 {
cpu-supply = <&reg_dcdc3>;
};
&de {
status = "okay";
};

8
arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
View File

@ -145,6 +145,14 @@
};
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&cpu100 {
cpu-supply = <&reg_dcdc3>;
};
&ehci0 {
/* GL830 USB-to-SATA bridge here */
status = "okay";

2
arch/arm/boot/dts/sun8i-a83t.dtsi
View File

@ -902,8 +902,6 @@
reset-names = "stmmaceth";
clocks = <&ccu 27>;
clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
mdio: mdio {

22
arch/arm/boot/dts/sun8i-h3.dtsi
View File

@ -111,6 +111,28 @@
};
soc {
system-control@1c00000 {
compatible = "allwinner,sun8i-h3-system-control";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram_c: sram@1d00000 {
compatible = "mmio-sram";
reg = <0x01d00000 0x80000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x01d00000 0x80000>;
ve_sram: sram-section@0 {
compatible = "allwinner,sun8i-h3-sram-c1",
"allwinner,sun4i-a10-sram-c1";
reg = <0x000000 0x80000>;
};
};
};
mali: gpu@1c40000 {
compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
reg = <0x01c40000 0x10000>;

29
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
View File

@ -59,6 +59,17 @@
stdout-path = "serial0:115200n8";
};
connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
@ -94,6 +105,10 @@
};
};
&de {
status = "okay";
};
&ehci1 {
status = "okay";
};
@ -118,6 +133,16 @@
};
};
&hdmi {
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&i2c0 {
status = "okay";
@ -226,6 +251,10 @@
regulator-name = "vcc-wifi";
};
&tcon_tv0 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;

319
arch/arm/boot/dts/sun8i-r40.dtsi
View File

@ -42,8 +42,10 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-r40-ccu.h>
#include <dt-bindings/reset/sun8i-r40-ccu.h>
#include <dt-bindings/reset/sun8i-de2.h>
/ {
#address-cells = <1>;
@ -99,12 +101,75 @@
};
};
de: display-engine {
compatible = "allwinner,sun8i-r40-display-engine";
allwinner,pipelines = <&mixer0>, <&mixer1>;
status = "disabled";
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
display_clocks: clock@1000000 {
compatible = "allwinner,sun8i-r40-de2-clk",
"allwinner,sun8i-h3-de2-clk";
reg = <0x01000000 0x100000>;
clocks = <&ccu CLK_DE>,
<&ccu CLK_BUS_DE>;
clock-names = "mod",
"bus";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
mixer0: mixer@1100000 {
compatible = "allwinner,sun8i-r40-de2-mixer-0";
reg = <0x01100000 0x100000>;
clocks = <&display_clocks CLK_BUS_MIXER0>,
<&display_clocks CLK_MIXER0>;
clock-names = "bus",
"mod";
resets = <&display_clocks RST_MIXER0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mixer0_out: port@1 {
reg = <1>;
mixer0_out_tcon_top: endpoint {
remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
};
};
};
};
mixer1: mixer@1200000 {
compatible = "allwinner,sun8i-r40-de2-mixer-1";
reg = <0x01200000 0x100000>;
clocks = <&display_clocks CLK_BUS_MIXER1>,
<&display_clocks CLK_MIXER1>;
clock-names = "bus",
"mod";
resets = <&display_clocks RST_WB>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mixer1_out: port@1 {
reg = <1>;
mixer1_out_tcon_top: endpoint {
remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
};
};
};
};
nmi_intc: interrupt-controller@1c00030 {
compatible = "allwinner,sun7i-a20-sc-nmi";
interrupt-controller;
@ -474,8 +539,6 @@
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_GMAC>;
clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
gmac_mdio: mdio {
@ -485,6 +548,213 @@
};
};
tcon_top: tcon-top@1c70000 {
compatible = "allwinner,sun8i-r40-tcon-top";
reg = <0x01c70000 0x1000>;
clocks = <&ccu CLK_BUS_TCON_TOP>,
<&ccu CLK_TCON_TV0>,
<&ccu CLK_TVE0>,
<&ccu CLK_TCON_TV1>,
<&ccu CLK_TVE1>,
<&ccu CLK_DSI_DPHY>;
clock-names = "bus",
"tcon-tv0",
"tve0",
"tcon-tv1",
"tve1",
"dsi";
clock-output-names = "tcon-top-tv0",
"tcon-top-tv1",
"tcon-top-dsi";
resets = <&ccu RST_BUS_TCON_TOP>;
#clock-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon_top_mixer0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
tcon_top_mixer0_in_mixer0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mixer0_out_tcon_top>;
};
};
tcon_top_mixer0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
reg = <0>;
};
tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
reg = <1>;
};
tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
reg = <2>;
remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
};
tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
reg = <3>;
remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
};
};
tcon_top_mixer1_in: port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
tcon_top_mixer1_in_mixer1: endpoint@1 {
reg = <1>;
remote-endpoint = <&mixer1_out_tcon_top>;
};
};
tcon_top_mixer1_out: port@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
reg = <0>;
};
tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
reg = <1>;
};
tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
reg = <2>;
remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
};
tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
reg = <3>;
remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
};
};
tcon_top_hdmi_in: port@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon_tv0_out_tcon_top>;
};
tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
reg = <1>;
remote-endpoint = <&tcon_tv1_out_tcon_top>;
};
};
tcon_top_hdmi_out: port@5 {
reg = <5>;
tcon_top_hdmi_out_hdmi: endpoint {
remote-endpoint = <&hdmi_in_tcon_top>;
};
};
};
};
tcon_tv0: lcd-controller@1c73000 {
compatible = "allwinner,sun8i-r40-tcon-tv";
reg = <0x01c73000 0x1000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
clock-names = "ahb", "tcon-ch1";
resets = <&ccu RST_BUS_TCON_TV0>;
reset-names = "lcd";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon_tv0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
};
tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
reg = <1>;
remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
};
};
tcon_tv0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
tcon_tv0_out_tcon_top: endpoint@1 {
reg = <1>;
remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
};
};
};
};
tcon_tv1: lcd-controller@1c74000 {
compatible = "allwinner,sun8i-r40-tcon-tv";
reg = <0x01c74000 0x1000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>;
clock-names = "ahb", "tcon-ch1";
resets = <&ccu RST_BUS_TCON_TV1>;
reset-names = "lcd";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon_tv1_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
};
tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
reg = <1>;
remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
};
};
tcon_tv1_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
tcon_tv1_out_tcon_top: endpoint@1 {
reg = <1>;
remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
};
};
};
};
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
@ -495,6 +765,51 @@
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
hdmi: hdmi@1ee0000 {
compatible = "allwinner,sun8i-r40-dw-hdmi",
"allwinner,sun8i-a83t-dw-hdmi";
reg = <0x01ee0000 0x10000>;
reg-io-width = <1>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
<&ccu CLK_HDMI>;
clock-names = "iahb", "isfr", "tmds";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;
phy-names = "hdmi-phy";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in: port@0 {
reg = <0>;
hdmi_in_tcon_top: endpoint {
remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
};
};
hdmi_out: port@1 {
reg = <1>;
};
};
};
hdmi_phy: hdmi-phy@1ef0000 {
compatible = "allwinner,sun8i-r40-hdmi-phy",
"allwinner,sun50i-a64-hdmi-phy";
reg = <0x01ef0000 0x10000>;
clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
<&ccu 7>, <&ccu 16>;
clock-names = "bus", "mod", "pll-0", "pll-1";
resets = <&ccu RST_BUS_HDMI0>;
reset-names = "phy";
#phy-cells = <0>;
};
};
timer {