(A bit late) first round of Samsung clock patches for v3.14.
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJSzZteAAoJEIv3Hb8G/XruMEEP/RBrOT1ohr5zbMGAg+rifLed 6y/EHayeP0GoHfbYlgmgiJaBzyglg/Q/zZKdRrAVGBq15PS6IcTiwocbYGv0omUA KpdwYkEBA0PEdubMxWDEjaXFBXSB+szkGJ64EJtOb17Jy0wurLphsD5vOI8xcwen accbiP0gXxNgFnrLxuwPoldRZu12EHdihGMynembs4PqBsLmTTX3s1V854aQdbYx 1JC4r8HxZ5O5pUyFiiKMms2gfxgS6DusVnbB9AO2cIGdqRyghT272DVsvbNoZ8Ek GDjKxc3bNBYnQdixYu3abz+ob3EjSqK2UKYILogM6WtTn6x3Wyn6u0s+6d7m8urj 0EYiIPElrnwWy7gPcZJmEyyxI7hRxQdOsAzYiV3tlNS+f/I6P0gLqk6CjjaAtCOs jZQGJxhAX8J2qici7OjijPs+Tt2a1Ruv9v3YPMted092ITRACq5SvOlQpHWSd1l/ WYhH/9nSCJuDO6pQo1K2PJoJKQ9Vl5YjxH73uvzRu7yQtA+BhuuM2r0YjovT3E8V 3NBGf2TS/HsbWQ68AnOrgDFvEqpW3AFci+6csw8WdLC/QZRuJIsQ/OArHNG3b01x VvD/39YED5nGOi2ZzJod6QS8xiNCB7enP19R6dDJRZcGxGKflLIZYjJCQNjZGDVN i5orwYDyFeziUW9WrjZO =vxZ7 -----END PGP SIGNATURE----- Merge tag 'for_3.14/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next-samsung (A bit late) first round of Samsung clock patches for v3.14.
This commit is contained in:
Mike Turquette
commit
baa39cd20e
|
|
@ -8,12 +8,29 @@ Required Properties:
|
|||
|
||||
- compatible: should be one of the following:
|
||||
- "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
|
||||
- "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.
|
||||
|
||||
- "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
|
||||
SoCs.
|
||||
- "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
|
||||
SoCs.
|
||||
- reg: physical base address and length of the controller's register set.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
- clocks:
|
||||
- pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
|
||||
is used if not specified.
|
||||
- pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
|
||||
is used if not specified.
|
||||
- cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
|
||||
specified.
|
||||
- sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
|
||||
not specified.
|
||||
- sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not
|
||||
specified.
|
||||
|
||||
- clock-names: Aliases for the above clocks. They should be "pll_ref",
|
||||
"pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
|
||||
|
||||
The following is the list of clocks generated by the controller. Each clock is
|
||||
assigned an identifier and client nodes use this identifier to specify the
|
||||
clock which they consume. Some of the clocks are available only on a particular
|
||||
|
|
@ -34,8 +51,10 @@ i2s_bus 6
|
|||
sclk_i2s 7
|
||||
pcm_bus 8
|
||||
sclk_pcm 9
|
||||
adma 10 Exynos5420
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
Example 1: An example of a clock controller node using the default input
|
||||
clock names is listed below.
|
||||
|
||||
clock_audss: audss-clock-controller@3810000 {
|
||||
compatible = "samsung,exynos5250-audss-clock";
|
||||
|
|
@ -43,7 +62,19 @@ clock_audss: audss-clock-controller@3810000 {
|
|||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: I2S controller node that consumes the clock generated by the clock
|
||||
Example 2: An example of a clock controller node with the input clocks
|
||||
specified.
|
||||
|
||||
clock_audss: audss-clock-controller@3810000 {
|
||||
compatible = "samsung,exynos5250-audss-clock";
|
||||
reg = <0x03810000 0x0C>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
|
||||
<&ext_i2s_clk>;
|
||||
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
|
||||
};
|
||||
|
||||
Example 3: I2S controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
||||
|
|
|
|||
|
|
@ -62,6 +62,7 @@ clock which they consume.
|
|||
div_i2s1 157
|
||||
div_i2s2 158
|
||||
sclk_hdmiphy 159
|
||||
div_pcm0 160
|
||||
|
||||
|
||||
[Peripheral Clock Gates]
|
||||
|
|
@ -159,6 +160,8 @@ clock which they consume.
|
|||
mixer 343
|
||||
hdmi 344
|
||||
g2d 345
|
||||
mdma0 346
|
||||
smmu_mdma0 347
|
||||
|
||||
|
||||
[Clock Muxes]
|
||||
|
|
|
|||
|
|
@ -88,6 +88,8 @@
|
|||
compatible = "samsung,exynos5250-audss-clock";
|
||||
reg = <0x03810000 0x0C>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>;
|
||||
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
|
||||
};
|
||||
|
||||
timer {
|
||||
|
|
@ -559,7 +561,7 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x10800000 0x1000>;
|
||||
interrupts = <0 33 0>;
|
||||
clocks = <&clock 271>;
|
||||
clocks = <&clock 346>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
|
|
|
|||
|
|
@ -76,8 +76,8 @@
|
|||
compatible = "samsung,exynos5420-audss-clock";
|
||||
reg = <0x03810000 0x0C>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clock 148>;
|
||||
clock-names = "sclk_audio";
|
||||
clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>;
|
||||
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
|
||||
};
|
||||
|
||||
codec@11000000 {
|
||||
|
|
|
|||
|
|
@ -14,9 +14,17 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <dt-bindings/clk/exynos-audss-clk.h>
|
||||
|
||||
enum exynos_audss_clk_type {
|
||||
TYPE_EXYNOS4210,
|
||||
TYPE_EXYNOS5250,
|
||||
TYPE_EXYNOS5420,
|
||||
};
|
||||
|
||||
static DEFINE_SPINLOCK(lock);
|
||||
static struct clk **clk_table;
|
||||
static void __iomem *reg_base;
|
||||
|
|
@ -26,17 +34,13 @@ static struct clk_onecell_data clk_data;
|
|||
#define ASS_CLK_DIV 0x4
|
||||
#define ASS_CLK_GATE 0x8
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static unsigned long reg_save[][2] = {
|
||||
{ASS_CLK_SRC, 0},
|
||||
{ASS_CLK_DIV, 0},
|
||||
{ASS_CLK_GATE, 0},
|
||||
};
|
||||
|
||||
/* list of all parent clock list */
|
||||
static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
|
||||
static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int exynos_audss_clk_suspend(void)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -61,31 +65,69 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
|
|||
};
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
static const struct of_device_id exynos_audss_clk_of_match[] = {
|
||||
{ .compatible = "samsung,exynos4210-audss-clock",
|
||||
.data = (void *)TYPE_EXYNOS4210, },
|
||||
{ .compatible = "samsung,exynos5250-audss-clock",
|
||||
.data = (void *)TYPE_EXYNOS5250, },
|
||||
{ .compatible = "samsung,exynos5420-audss-clock",
|
||||
.data = (void *)TYPE_EXYNOS5420, },
|
||||
{},
|
||||
};
|
||||
|
||||
/* register exynos_audss clocks */
|
||||
static void __init exynos_audss_clk_init(struct device_node *np)
|
||||
static int exynos_audss_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base) {
|
||||
pr_err("%s: failed to map audss registers\n", __func__);
|
||||
return;
|
||||
int i, ret = 0;
|
||||
struct resource *res;
|
||||
const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
|
||||
const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
|
||||
const char *sclk_pcm_p = "sclk_pcm0";
|
||||
struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
|
||||
const struct of_device_id *match;
|
||||
enum exynos_audss_clk_type variant;
|
||||
|
||||
match = of_match_node(exynos_audss_clk_of_match, pdev->dev.of_node);
|
||||
if (!match)
|
||||
return -EINVAL;
|
||||
variant = (enum exynos_audss_clk_type)match->data;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
reg_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(reg_base)) {
|
||||
dev_err(&pdev->dev, "failed to map audss registers\n");
|
||||
return PTR_ERR(reg_base);
|
||||
}
|
||||
|
||||
clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
|
||||
clk_table = devm_kzalloc(&pdev->dev,
|
||||
sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
|
||||
GFP_KERNEL);
|
||||
if (!clk_table) {
|
||||
pr_err("%s: could not allocate clk lookup table\n", __func__);
|
||||
return;
|
||||
}
|
||||
if (!clk_table)
|
||||
return -ENOMEM;
|
||||
|
||||
clk_data.clks = clk_table;
|
||||
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
if (variant == TYPE_EXYNOS5420)
|
||||
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
|
||||
else
|
||||
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1;
|
||||
|
||||
pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
|
||||
pll_in = devm_clk_get(&pdev->dev, "pll_in");
|
||||
if (!IS_ERR(pll_ref))
|
||||
mout_audss_p[0] = __clk_get_name(pll_ref);
|
||||
if (!IS_ERR(pll_in))
|
||||
mout_audss_p[1] = __clk_get_name(pll_in);
|
||||
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
|
||||
mout_audss_p, ARRAY_SIZE(mout_audss_p),
|
||||
CLK_SET_RATE_NO_REPARENT,
|
||||
reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
|
||||
|
||||
cdclk = devm_clk_get(&pdev->dev, "cdclk");
|
||||
sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio");
|
||||
if (!IS_ERR(cdclk))
|
||||
mout_i2s_p[1] = __clk_get_name(cdclk);
|
||||
if (!IS_ERR(sclk_audio))
|
||||
mout_i2s_p[2] = __clk_get_name(sclk_audio);
|
||||
clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
|
||||
mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
|
||||
CLK_SET_RATE_NO_REPARENT,
|
||||
|
|
@ -119,17 +161,88 @@ static void __init exynos_audss_clk_init(struct device_node *np)
|
|||
"sclk_pcm", CLK_SET_RATE_PARENT,
|
||||
reg_base + ASS_CLK_GATE, 4, 0, &lock);
|
||||
|
||||
sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in");
|
||||
if (!IS_ERR(sclk_pcm_in))
|
||||
sclk_pcm_p = __clk_get_name(sclk_pcm_in);
|
||||
clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
|
||||
"div_pcm0", CLK_SET_RATE_PARENT,
|
||||
sclk_pcm_p, CLK_SET_RATE_PARENT,
|
||||
reg_base + ASS_CLK_GATE, 5, 0, &lock);
|
||||
|
||||
if (variant == TYPE_EXYNOS5420) {
|
||||
clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
|
||||
"dout_srp", CLK_SET_RATE_PARENT,
|
||||
reg_base + ASS_CLK_GATE, 9, 0, &lock);
|
||||
}
|
||||
|
||||
for (i = 0; i < clk_data.clk_num; i++) {
|
||||
if (IS_ERR(clk_table[i])) {
|
||||
dev_err(&pdev->dev, "failed to register clock %d\n", i);
|
||||
ret = PTR_ERR(clk_table[i]);
|
||||
goto unregister;
|
||||
}
|
||||
}
|
||||
|
||||
ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
|
||||
&clk_data);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to add clock provider\n");
|
||||
goto unregister;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
register_syscore_ops(&exynos_audss_clk_syscore_ops);
|
||||
#endif
|
||||
|
||||
pr_info("Exynos: Audss: clock setup completed\n");
|
||||
dev_info(&pdev->dev, "setup completed\n");
|
||||
|
||||
return 0;
|
||||
|
||||
unregister:
|
||||
for (i = 0; i < clk_data.clk_num; i++) {
|
||||
if (!IS_ERR(clk_table[i]))
|
||||
clk_unregister(clk_table[i]);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
|
||||
exynos_audss_clk_init);
|
||||
CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
|
||||
exynos_audss_clk_init);
|
||||
|
||||
static int exynos_audss_clk_remove(struct platform_device *pdev)
|
||||
{
|
||||
int i;
|
||||
|
||||
of_clk_del_provider(pdev->dev.of_node);
|
||||
|
||||
for (i = 0; i < clk_data.clk_num; i++) {
|
||||
if (!IS_ERR(clk_table[i]))
|
||||
clk_unregister(clk_table[i]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver exynos_audss_clk_driver = {
|
||||
.driver = {
|
||||
.name = "exynos-audss-clk",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = exynos_audss_clk_of_match,
|
||||
},
|
||||
.probe = exynos_audss_clk_probe,
|
||||
.remove = exynos_audss_clk_remove,
|
||||
};
|
||||
|
||||
static int __init exynos_audss_clk_init(void)
|
||||
{
|
||||
return platform_driver_register(&exynos_audss_clk_driver);
|
||||
}
|
||||
core_initcall(exynos_audss_clk_init);
|
||||
|
||||
static void __exit exynos_audss_clk_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&exynos_audss_clk_driver);
|
||||
}
|
||||
module_exit(exynos_audss_clk_exit);
|
||||
|
||||
MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
|
||||
MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:exynos-audss-clk");
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,6 +10,7 @@
|
|||
* Common Clock Framework support for Exynos5250 SoC.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/exynos5250.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
|
@ -25,6 +26,7 @@
|
|||
#define MPLL_LOCK 0x4000
|
||||
#define MPLL_CON0 0x4100
|
||||
#define SRC_CORE1 0x4204
|
||||
#define GATE_IP_ACP 0x8800
|
||||
#define CPLL_LOCK 0x10020
|
||||
#define EPLL_LOCK 0x10030
|
||||
#define VPLL_LOCK 0x10040
|
||||
|
|
@ -35,6 +37,7 @@
|
|||
#define GPLL_CON0 0x10150
|
||||
#define SRC_TOP0 0x10210
|
||||
#define SRC_TOP2 0x10218
|
||||
#define SRC_TOP3 0x1021c
|
||||
#define SRC_GSCL 0x10220
|
||||
#define SRC_DISP1_0 0x1022c
|
||||
#define SRC_MAU 0x10240
|
||||
|
|
@ -65,6 +68,7 @@
|
|||
#define DIV_PERIC4 0x10568
|
||||
#define DIV_PERIC5 0x1056c
|
||||
#define GATE_IP_GSCL 0x10920
|
||||
#define GATE_IP_DISP1 0x10928
|
||||
#define GATE_IP_MFC 0x1092c
|
||||
#define GATE_IP_GEN 0x10934
|
||||
#define GATE_IP_FSYS 0x10944
|
||||
|
|
@ -74,8 +78,6 @@
|
|||
#define BPLL_CON0 0x20110
|
||||
#define SRC_CDREX 0x20200
|
||||
#define PLL_DIV2_SEL 0x20a24
|
||||
#define GATE_IP_DISP1 0x10928
|
||||
#define GATE_IP_ACP 0x10000
|
||||
|
||||
/* list of PLLs to be registered */
|
||||
enum exynos5250_plls {
|
||||
|
|
@ -83,51 +85,6 @@ enum exynos5250_plls {
|
|||
nr_plls /* number of PLLs */
|
||||
};
|
||||
|
||||
/*
|
||||
* Let each supported clock get a unique id. This id is used to lookup the clock
|
||||
* for device tree based platforms. The clocks are categorized into three
|
||||
* sections: core, sclk gate and bus interface gate clocks.
|
||||
*
|
||||
* When adding a new clock to this list, it is advised to choose a clock
|
||||
* category and add it to the end of that category. That is because the the
|
||||
* device tree source file is referring to these ids and any change in the
|
||||
* sequence number of existing clocks will require corresponding change in the
|
||||
* device tree files. This limitation would go away when pre-processor support
|
||||
* for dtc would be available.
|
||||
*/
|
||||
enum exynos5250_clks {
|
||||
none,
|
||||
|
||||
/* core clocks */
|
||||
fin_pll, fout_apll, fout_mpll, fout_bpll, fout_gpll, fout_cpll,
|
||||
fout_epll, fout_vpll,
|
||||
|
||||
/* gate for special clocks (sclk) */
|
||||
sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb,
|
||||
sclk_fimd1, sclk_mipi1, sclk_dp, sclk_hdmi, sclk_pixel, sclk_audio0,
|
||||
sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
|
||||
sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
|
||||
sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
|
||||
div_i2s1, div_i2s2, sclk_hdmiphy,
|
||||
|
||||
/* gate clocks */
|
||||
gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
|
||||
smmu_gscl1, smmu_gscl2, smmu_gscl3, mfc, smmu_mfcl, smmu_mfcr, rotator,
|
||||
jpeg, mdma1, smmu_rotator, smmu_jpeg, smmu_mdma1, pdma0, pdma1, sata,
|
||||
usbotg, mipi_hsi, sdmmc0, sdmmc1, sdmmc2, sdmmc3, sromc, usb2, usb3,
|
||||
sata_phyctrl, sata_phyi2c, uart0, uart1, uart2, uart3, uart4, i2c0,
|
||||
i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, adc, spi0, spi1,
|
||||
spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
|
||||
hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
|
||||
tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
|
||||
wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
|
||||
|
||||
/* mux clocks */
|
||||
mout_hdmi = 1024,
|
||||
|
||||
nr_clks,
|
||||
};
|
||||
|
||||
/*
|
||||
* list of controller registers to be saved and restored during a
|
||||
* suspend/resume cycle.
|
||||
|
|
@ -138,6 +95,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
|
|||
SRC_CORE1,
|
||||
SRC_TOP0,
|
||||
SRC_TOP2,
|
||||
SRC_TOP3,
|
||||
SRC_GSCL,
|
||||
SRC_DISP1_0,
|
||||
SRC_MAU,
|
||||
|
|
@ -181,7 +139,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
|
|||
|
||||
/* list of all parent clock list */
|
||||
PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
|
||||
PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
|
||||
PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
|
||||
PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
|
||||
PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
|
||||
PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
|
||||
|
|
@ -190,308 +148,432 @@ PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
|
|||
PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
|
||||
PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
|
||||
PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
|
||||
PNAME(mout_mpll_user_p) = { "fin_pll", "sclk_mpll" };
|
||||
PNAME(mout_bpll_user_p) = { "fin_pll", "sclk_bpll" };
|
||||
PNAME(mout_aclk166_p) = { "sclk_cpll", "sclk_mpll_user" };
|
||||
PNAME(mout_aclk200_p) = { "sclk_mpll_user", "sclk_bpll_user" };
|
||||
PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" };
|
||||
PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" };
|
||||
PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" };
|
||||
PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" };
|
||||
PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
|
||||
PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
|
||||
PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
|
||||
PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
|
||||
PNAME(mout_usb3_p) = { "sclk_mpll_user", "sclk_cpll" };
|
||||
PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" };
|
||||
PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
|
||||
"sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
|
||||
"sclk_mpll_user", "sclk_epll", "sclk_vpll",
|
||||
"sclk_cpll" };
|
||||
"mout_mpll_user", "mout_epll", "mout_vpll",
|
||||
"mout_cpll", "none", "none",
|
||||
"none", "none", "none",
|
||||
"none" };
|
||||
PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
|
||||
"sclk_uhostphy", "sclk_hdmiphy",
|
||||
"sclk_mpll_user", "sclk_epll", "sclk_vpll",
|
||||
"sclk_cpll" };
|
||||
"sclk_uhostphy", "fin_pll",
|
||||
"mout_mpll_user", "mout_epll", "mout_vpll",
|
||||
"mout_cpll", "none", "none",
|
||||
"none", "none", "none",
|
||||
"none" };
|
||||
PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
|
||||
"sclk_uhostphy", "sclk_hdmiphy",
|
||||
"sclk_mpll_user", "sclk_epll", "sclk_vpll",
|
||||
"sclk_cpll" };
|
||||
"sclk_uhostphy", "fin_pll",
|
||||
"mout_mpll_user", "mout_epll", "mout_vpll",
|
||||
"mout_cpll", "none", "none",
|
||||
"none", "none", "none",
|
||||
"none" };
|
||||
PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
|
||||
"sclk_uhostphy", "sclk_hdmiphy",
|
||||
"sclk_mpll_user", "sclk_epll", "sclk_vpll",
|
||||
"sclk_cpll" };
|
||||
"sclk_uhostphy", "fin_pll",
|
||||
"mout_mpll_user", "mout_epll", "mout_vpll",
|
||||
"mout_cpll", "none", "none",
|
||||
"none", "none", "none",
|
||||
"none" };
|
||||
PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
|
||||
"spdif_extclk" };
|
||||
|
||||
/* fixed rate clocks generated outside the soc */
|
||||
static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
|
||||
FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
|
||||
FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
|
||||
};
|
||||
|
||||
/* fixed rate clocks generated inside the soc */
|
||||
static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
|
||||
FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
|
||||
FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
|
||||
FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
|
||||
FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
|
||||
FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
|
||||
FRATE(0, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
|
||||
FRATE(0, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
|
||||
FRATE(0, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
|
||||
};
|
||||
|
||||
static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
|
||||
FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
|
||||
FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
|
||||
FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
|
||||
FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = {
|
||||
MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
|
||||
MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
|
||||
MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"),
|
||||
MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
|
||||
MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
|
||||
MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
|
||||
MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
|
||||
MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
|
||||
MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
|
||||
MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1),
|
||||
MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
|
||||
MUX(none, "sclk_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
|
||||
MUX(none, "sclk_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
|
||||
MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
|
||||
MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
|
||||
MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
|
||||
MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
|
||||
MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
|
||||
MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
|
||||
MUX(none, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
|
||||
MUX(none, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
|
||||
MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
|
||||
MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
|
||||
MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
|
||||
MUX(mout_hdmi, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
|
||||
MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
|
||||
MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
|
||||
MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
|
||||
MUX(none, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
|
||||
MUX(none, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
|
||||
MUX(none, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
|
||||
MUX(none, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
|
||||
MUX(none, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
|
||||
MUX(none, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
|
||||
MUX(none, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
|
||||
MUX(none, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
|
||||
MUX(none, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
|
||||
MUX(none, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
|
||||
MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
|
||||
MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
|
||||
MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
|
||||
MUX(none, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
|
||||
MUX(none, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
|
||||
MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
|
||||
/*
|
||||
* NOTE: Following table is sorted by (clock domain, register address,
|
||||
* bitfield shift) triplet in ascending order. When adding new entries,
|
||||
* please make sure that the order is kept, to avoid merge conflicts
|
||||
* and make further work with defined data easier.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMU_CPU
|
||||
*/
|
||||
MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
|
||||
CLK_SET_RATE_PARENT, 0, "mout_apll"),
|
||||
MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
|
||||
|
||||
/*
|
||||
* CMU_CORE
|
||||
*/
|
||||
MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
|
||||
|
||||
/*
|
||||
* CMU_TOP
|
||||
*/
|
||||
MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
|
||||
MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
|
||||
MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
|
||||
|
||||
MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
|
||||
MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
|
||||
MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
|
||||
MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
|
||||
MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
|
||||
|
||||
MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1),
|
||||
MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
|
||||
MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1),
|
||||
|
||||
MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
|
||||
MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
|
||||
MUX(0, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
|
||||
MUX(0, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
|
||||
MUX(0, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
|
||||
|
||||
MUX(0, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
|
||||
MUX(0, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
|
||||
MUX(0, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
|
||||
MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
|
||||
|
||||
MUX(0, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
|
||||
|
||||
MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
|
||||
MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
|
||||
MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
|
||||
MUX(0, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
|
||||
MUX(0, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
|
||||
MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
|
||||
|
||||
MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
|
||||
|
||||
MUX(0, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
|
||||
MUX(0, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
|
||||
MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
|
||||
MUX(0, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
|
||||
MUX(0, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
|
||||
|
||||
MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
|
||||
MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
|
||||
MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
|
||||
MUX(0, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
|
||||
MUX(0, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
|
||||
MUX(0, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
|
||||
|
||||
/*
|
||||
* CMU_CDREX
|
||||
*/
|
||||
MUX(0, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
|
||||
|
||||
MUX(0, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
|
||||
MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
|
||||
};
|
||||
|
||||
static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
|
||||
DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
|
||||
DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
|
||||
DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3),
|
||||
DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
|
||||
DIV(none, "aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3),
|
||||
DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
|
||||
DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
|
||||
DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
|
||||
DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
|
||||
DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
|
||||
DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
|
||||
DIV(none, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
|
||||
DIV(none, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
|
||||
DIV(none, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
|
||||
DIV(none, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
|
||||
DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
|
||||
DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
|
||||
DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
|
||||
DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
|
||||
DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
|
||||
DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
|
||||
DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
|
||||
DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
|
||||
DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
|
||||
DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
|
||||
DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
|
||||
DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
|
||||
DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
|
||||
DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
|
||||
DIV(none, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
|
||||
DIV(none, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
|
||||
DIV(none, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
|
||||
DIV(none, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
|
||||
DIV(none, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
|
||||
DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
|
||||
DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
|
||||
DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
|
||||
DIV(div_i2s1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
|
||||
DIV(div_i2s2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
|
||||
DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
|
||||
DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
|
||||
DIV_F(none, "div_mipi1_pre", "div_mipi1",
|
||||
/*
|
||||
* NOTE: Following table is sorted by (clock domain, register address,
|
||||
* bitfield shift) triplet in ascending order. When adding new entries,
|
||||
* please make sure that the order is kept, to avoid merge conflicts
|
||||
* and make further work with defined data easier.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMU_CPU
|
||||
*/
|
||||
DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
|
||||
DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
|
||||
DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
|
||||
|
||||
/*
|
||||
* CMU_TOP
|
||||
*/
|
||||
DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3),
|
||||
DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
|
||||
DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
|
||||
DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
|
||||
DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
|
||||
|
||||
DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
|
||||
|
||||
DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
|
||||
DIV(0, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
|
||||
DIV(0, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
|
||||
DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
|
||||
DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
|
||||
|
||||
DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
|
||||
DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
|
||||
DIV_F(0, "div_mipi1_pre", "div_mipi1",
|
||||
DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
|
||||
DIV_F(none, "div_mmc_pre0", "div_mmc0",
|
||||
DIV(0, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
|
||||
DIV(CLK_SCLK_PIXEL, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4),
|
||||
|
||||
DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
|
||||
|
||||
DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
|
||||
DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
|
||||
|
||||
DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
|
||||
DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
|
||||
|
||||
DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
|
||||
DIV_F(0, "div_mmc_pre0", "div_mmc0",
|
||||
DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
|
||||
DIV_F(none, "div_mmc_pre1", "div_mmc1",
|
||||
DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
|
||||
DIV_F(0, "div_mmc_pre1", "div_mmc1",
|
||||
DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
|
||||
DIV_F(none, "div_mmc_pre2", "div_mmc2",
|
||||
|
||||
DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
|
||||
DIV_F(0, "div_mmc_pre2", "div_mmc2",
|
||||
DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
|
||||
DIV_F(none, "div_mmc_pre3", "div_mmc3",
|
||||
DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
|
||||
DIV_F(0, "div_mmc_pre3", "div_mmc3",
|
||||
DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
|
||||
DIV_F(none, "div_spi_pre0", "div_spi0",
|
||||
|
||||
DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
|
||||
DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
|
||||
DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
|
||||
DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
|
||||
|
||||
DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
|
||||
DIV_F(0, "div_spi_pre0", "div_spi0",
|
||||
DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
|
||||
DIV_F(none, "div_spi_pre1", "div_spi1",
|
||||
DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
|
||||
DIV_F(0, "div_spi_pre1", "div_spi1",
|
||||
DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
|
||||
DIV_F(none, "div_spi_pre2", "div_spi2",
|
||||
|
||||
DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
|
||||
DIV_F(0, "div_spi_pre2", "div_spi2",
|
||||
DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
|
||||
|
||||
DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
|
||||
|
||||
DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
|
||||
DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
|
||||
DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
|
||||
DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
|
||||
|
||||
DIV(CLK_DIV_I2S1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
|
||||
DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
|
||||
GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0),
|
||||
GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0),
|
||||
GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0),
|
||||
GATE(gscl3, "gscl3", "aclk266", GATE_IP_GSCL, 3, 0, 0),
|
||||
GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
|
||||
GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
|
||||
GATE(smmu_gscl0, "smmu_gscl0", "aclk266", GATE_IP_GSCL, 7, 0, 0),
|
||||
GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0),
|
||||
GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0),
|
||||
GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0),
|
||||
GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
|
||||
GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
|
||||
GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
|
||||
GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
|
||||
GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0),
|
||||
GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
|
||||
GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
|
||||
GATE(smmu_jpeg, "smmu_jpeg", "aclk166", GATE_IP_GEN, 7, 0, 0),
|
||||
GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
|
||||
GATE(pdma0, "pdma0", "aclk200", GATE_IP_FSYS, 1, 0, 0),
|
||||
GATE(pdma1, "pdma1", "aclk200", GATE_IP_FSYS, 2, 0, 0),
|
||||
GATE(sata, "sata", "aclk200", GATE_IP_FSYS, 6, 0, 0),
|
||||
GATE(usbotg, "usbotg", "aclk200", GATE_IP_FSYS, 7, 0, 0),
|
||||
GATE(mipi_hsi, "mipi_hsi", "aclk200", GATE_IP_FSYS, 8, 0, 0),
|
||||
GATE(sdmmc0, "sdmmc0", "aclk200", GATE_IP_FSYS, 12, 0, 0),
|
||||
GATE(sdmmc1, "sdmmc1", "aclk200", GATE_IP_FSYS, 13, 0, 0),
|
||||
GATE(sdmmc2, "sdmmc2", "aclk200", GATE_IP_FSYS, 14, 0, 0),
|
||||
GATE(sdmmc3, "sdmmc3", "aclk200", GATE_IP_FSYS, 15, 0, 0),
|
||||
GATE(sromc, "sromc", "aclk200", GATE_IP_FSYS, 17, 0, 0),
|
||||
GATE(usb2, "usb2", "aclk200", GATE_IP_FSYS, 18, 0, 0),
|
||||
GATE(usb3, "usb3", "aclk200", GATE_IP_FSYS, 19, 0, 0),
|
||||
GATE(sata_phyctrl, "sata_phyctrl", "aclk200", GATE_IP_FSYS, 24, 0, 0),
|
||||
GATE(sata_phyi2c, "sata_phyi2c", "aclk200", GATE_IP_FSYS, 25, 0, 0),
|
||||
GATE(uart0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
|
||||
GATE(uart1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
|
||||
GATE(uart2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
|
||||
GATE(uart3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
|
||||
GATE(uart4, "uart4", "aclk66", GATE_IP_PERIC, 4, 0, 0),
|
||||
GATE(i2c0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
|
||||
GATE(i2c1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
|
||||
GATE(i2c2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
|
||||
GATE(i2c3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
|
||||
GATE(i2c4, "i2c4", "aclk66", GATE_IP_PERIC, 10, 0, 0),
|
||||
GATE(i2c5, "i2c5", "aclk66", GATE_IP_PERIC, 11, 0, 0),
|
||||
GATE(i2c6, "i2c6", "aclk66", GATE_IP_PERIC, 12, 0, 0),
|
||||
GATE(i2c7, "i2c7", "aclk66", GATE_IP_PERIC, 13, 0, 0),
|
||||
GATE(i2c_hdmi, "i2c_hdmi", "aclk66", GATE_IP_PERIC, 14, 0, 0),
|
||||
GATE(adc, "adc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
|
||||
GATE(spi0, "spi0", "aclk66", GATE_IP_PERIC, 16, 0, 0),
|
||||
GATE(spi1, "spi1", "aclk66", GATE_IP_PERIC, 17, 0, 0),
|
||||
GATE(spi2, "spi2", "aclk66", GATE_IP_PERIC, 18, 0, 0),
|
||||
GATE(i2s1, "i2s1", "aclk66", GATE_IP_PERIC, 20, 0, 0),
|
||||
GATE(i2s2, "i2s2", "aclk66", GATE_IP_PERIC, 21, 0, 0),
|
||||
GATE(pcm1, "pcm1", "aclk66", GATE_IP_PERIC, 22, 0, 0),
|
||||
GATE(pcm2, "pcm2", "aclk66", GATE_IP_PERIC, 23, 0, 0),
|
||||
GATE(pwm, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
|
||||
GATE(spdif, "spdif", "aclk66", GATE_IP_PERIC, 26, 0, 0),
|
||||
GATE(ac97, "ac97", "aclk66", GATE_IP_PERIC, 27, 0, 0),
|
||||
GATE(hsi2c0, "hsi2c0", "aclk66", GATE_IP_PERIC, 28, 0, 0),
|
||||
GATE(hsi2c1, "hsi2c1", "aclk66", GATE_IP_PERIC, 29, 0, 0),
|
||||
GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
|
||||
GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
|
||||
GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
|
||||
GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
|
||||
GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
|
||||
GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
|
||||
GATE(tzpc2, "tzpc2", "aclk66", GATE_IP_PERIS, 8, 0, 0),
|
||||
GATE(tzpc3, "tzpc3", "aclk66", GATE_IP_PERIS, 9, 0, 0),
|
||||
GATE(tzpc4, "tzpc4", "aclk66", GATE_IP_PERIS, 10, 0, 0),
|
||||
GATE(tzpc5, "tzpc5", "aclk66", GATE_IP_PERIS, 11, 0, 0),
|
||||
GATE(tzpc6, "tzpc6", "aclk66", GATE_IP_PERIS, 12, 0, 0),
|
||||
GATE(tzpc7, "tzpc7", "aclk66", GATE_IP_PERIS, 13, 0, 0),
|
||||
GATE(tzpc8, "tzpc8", "aclk66", GATE_IP_PERIS, 14, 0, 0),
|
||||
GATE(tzpc9, "tzpc9", "aclk66", GATE_IP_PERIS, 15, 0, 0),
|
||||
GATE(hdmi_cec, "hdmi_cec", "aclk66", GATE_IP_PERIS, 16, 0, 0),
|
||||
GATE(mct, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
|
||||
GATE(wdt, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
|
||||
GATE(rtc, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
|
||||
GATE(tmu, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
|
||||
GATE(cmu_top, "cmu_top", "aclk66",
|
||||
GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(cmu_core, "cmu_core", "aclk66",
|
||||
GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(cmu_mem, "cmu_mem", "aclk66",
|
||||
GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(sclk_cam_bayer, "sclk_cam_bayer", "div_cam_bayer",
|
||||
/*
|
||||
* NOTE: Following table is sorted by (clock domain, register address,
|
||||
* bitfield shift) triplet in ascending order. When adding new entries,
|
||||
* please make sure that the order is kept, to avoid merge conflicts
|
||||
* and make further work with defined data easier.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMU_ACP
|
||||
*/
|
||||
GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
|
||||
GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
|
||||
GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
|
||||
|
||||
/*
|
||||
* CMU_TOP
|
||||
*/
|
||||
GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer",
|
||||
SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_cam0, "sclk_cam0", "div_cam0",
|
||||
GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0",
|
||||
SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_cam1, "sclk_cam1", "div_cam1",
|
||||
GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
|
||||
SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_gscl_wa, "sclk_gscl_wa", "div_gscl_wa",
|
||||
GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa",
|
||||
SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_gscl_wb, "sclk_gscl_wb", "div_gscl_wb",
|
||||
GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb",
|
||||
SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1",
|
||||
|
||||
GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1",
|
||||
SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_mipi1, "sclk_mipi1", "div_mipi1",
|
||||
GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi1",
|
||||
SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_dp, "sclk_dp", "div_dp",
|
||||
GATE(CLK_SCLK_DP, "sclk_dp", "div_dp",
|
||||
SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
|
||||
GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
|
||||
SRC_MASK_DISP1_0, 20, 0, 0),
|
||||
GATE(sclk_audio0, "sclk_audio0", "div_audio0",
|
||||
|
||||
GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
|
||||
SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0",
|
||||
|
||||
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
|
||||
SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1",
|
||||
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
|
||||
SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2",
|
||||
GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
|
||||
SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3",
|
||||
GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3",
|
||||
SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_sata, "sclk_sata", "div_sata",
|
||||
GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
|
||||
SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_usb3, "sclk_usb3", "div_usb3",
|
||||
GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3",
|
||||
SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_jpeg, "sclk_jpeg", "div_jpeg",
|
||||
|
||||
GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
|
||||
SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_uart0, "sclk_uart0", "div_uart0",
|
||||
|
||||
GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
|
||||
SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_uart1, "sclk_uart1", "div_uart1",
|
||||
GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
|
||||
SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_uart2, "sclk_uart2", "div_uart2",
|
||||
GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
|
||||
SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_uart3, "sclk_uart3", "div_uart3",
|
||||
GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
|
||||
SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_pwm, "sclk_pwm", "div_pwm",
|
||||
GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm",
|
||||
SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_audio1, "sclk_audio1", "div_audio1",
|
||||
|
||||
GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
|
||||
SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_audio2, "sclk_audio2", "div_audio2",
|
||||
GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
|
||||
SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
|
||||
GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
|
||||
SRC_MASK_PERIC1, 4, 0, 0),
|
||||
GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0",
|
||||
GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0",
|
||||
SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1",
|
||||
GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1",
|
||||
SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2",
|
||||
GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2",
|
||||
SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(fimd1, "fimd1", "aclk200", GATE_IP_DISP1, 0, 0, 0),
|
||||
GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0),
|
||||
GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0),
|
||||
GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
|
||||
GATE(mixer, "mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
|
||||
GATE(hdmi, "hdmi", "mout_aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
|
||||
GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0),
|
||||
|
||||
GATE(CLK_GSCL0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0,
|
||||
0),
|
||||
GATE(CLK_GSCL1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0,
|
||||
0),
|
||||
GATE(CLK_GSCL2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0,
|
||||
0),
|
||||
GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0,
|
||||
0),
|
||||
GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
|
||||
GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
|
||||
GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub",
|
||||
GATE_IP_GSCL, 7, 0, 0),
|
||||
GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub",
|
||||
GATE_IP_GSCL, 8, 0, 0),
|
||||
GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub",
|
||||
GATE_IP_GSCL, 9, 0, 0),
|
||||
GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub",
|
||||
GATE_IP_GSCL, 10, 0, 0),
|
||||
|
||||
GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0,
|
||||
0),
|
||||
GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0,
|
||||
0),
|
||||
GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0,
|
||||
0),
|
||||
GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0),
|
||||
GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0,
|
||||
0),
|
||||
GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0,
|
||||
0),
|
||||
|
||||
GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),
|
||||
GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0,
|
||||
0),
|
||||
GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
|
||||
0),
|
||||
|
||||
GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
|
||||
GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
|
||||
GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),
|
||||
GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0,
|
||||
0),
|
||||
GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0),
|
||||
GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0),
|
||||
|
||||
GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0),
|
||||
GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0),
|
||||
GATE(CLK_SATA, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0),
|
||||
GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0),
|
||||
GATE(CLK_MIPI_HSI, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0),
|
||||
GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
|
||||
GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0),
|
||||
GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0),
|
||||
GATE(CLK_SDMMC3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0),
|
||||
GATE(CLK_SROMC, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0),
|
||||
GATE(CLK_USB2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0),
|
||||
GATE(CLK_USB3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0),
|
||||
GATE(CLK_SATA_PHYCTRL, "sata_phyctrl", "div_aclk200",
|
||||
GATE_IP_FSYS, 24, 0, 0),
|
||||
GATE(CLK_SATA_PHYI2C, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0,
|
||||
0),
|
||||
|
||||
GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
|
||||
GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
|
||||
GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
|
||||
GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0),
|
||||
GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0),
|
||||
GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0),
|
||||
GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0),
|
||||
GATE(CLK_I2C2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0),
|
||||
GATE(CLK_I2C3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0),
|
||||
GATE(CLK_I2C4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0),
|
||||
GATE(CLK_I2C5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0),
|
||||
GATE(CLK_I2C6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0),
|
||||
GATE(CLK_I2C7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0),
|
||||
GATE(CLK_I2C_HDMI, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0),
|
||||
GATE(CLK_ADC, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0),
|
||||
GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0),
|
||||
GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0),
|
||||
GATE(CLK_SPI2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0),
|
||||
GATE(CLK_I2S1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0),
|
||||
GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0),
|
||||
GATE(CLK_PCM1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0),
|
||||
GATE(CLK_PCM2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0),
|
||||
GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0),
|
||||
GATE(CLK_SPDIF, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0),
|
||||
GATE(CLK_AC97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0),
|
||||
GATE(CLK_HSI2C0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0),
|
||||
GATE(CLK_HSI2C1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0),
|
||||
GATE(CLK_HSI2C2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0),
|
||||
GATE(CLK_HSI2C3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0),
|
||||
|
||||
GATE(CLK_CHIPID, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0),
|
||||
GATE(CLK_SYSREG, "sysreg", "div_aclk66",
|
||||
GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED,
|
||||
0),
|
||||
GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66",
|
||||
GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66",
|
||||
GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_CMU_MEM, "cmu_mem", "div_aclk66",
|
||||
GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_TZPC0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0),
|
||||
GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0),
|
||||
GATE(CLK_TZPC2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0),
|
||||
GATE(CLK_TZPC3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0),
|
||||
GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0),
|
||||
GATE(CLK_TZPC5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0),
|
||||
GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0),
|
||||
GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0),
|
||||
GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0),
|
||||
GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0),
|
||||
GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0),
|
||||
GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
|
||||
GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
|
||||
GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
|
||||
GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
|
||||
};
|
||||
|
||||
static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
|
||||
|
|
@ -517,20 +599,41 @@ static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = {
|
|||
{ },
|
||||
};
|
||||
|
||||
static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = {
|
||||
/* sorted in descending order */
|
||||
/* PLL_35XX_RATE(rate, m, p, s) */
|
||||
PLL_35XX_RATE(1700000000, 425, 6, 0),
|
||||
PLL_35XX_RATE(1600000000, 200, 3, 0),
|
||||
PLL_35XX_RATE(1500000000, 250, 4, 0),
|
||||
PLL_35XX_RATE(1400000000, 175, 3, 0),
|
||||
PLL_35XX_RATE(1300000000, 325, 6, 0),
|
||||
PLL_35XX_RATE(1200000000, 200, 4, 0),
|
||||
PLL_35XX_RATE(1100000000, 275, 6, 0),
|
||||
PLL_35XX_RATE(1000000000, 125, 3, 0),
|
||||
PLL_35XX_RATE(900000000, 150, 4, 0),
|
||||
PLL_35XX_RATE(800000000, 100, 3, 0),
|
||||
PLL_35XX_RATE(700000000, 175, 3, 1),
|
||||
PLL_35XX_RATE(600000000, 200, 4, 1),
|
||||
PLL_35XX_RATE(500000000, 125, 3, 1),
|
||||
PLL_35XX_RATE(400000000, 100, 3, 1),
|
||||
PLL_35XX_RATE(300000000, 200, 4, 2),
|
||||
PLL_35XX_RATE(200000000, 100, 3, 2),
|
||||
};
|
||||
|
||||
static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
|
||||
[apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
|
||||
APLL_CON0, "fout_apll", NULL),
|
||||
[mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK,
|
||||
MPLL_CON0, "fout_mpll", NULL),
|
||||
[bpll] = PLL(pll_35xx, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK,
|
||||
[apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
|
||||
APLL_LOCK, APLL_CON0, "fout_apll", NULL),
|
||||
[mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
|
||||
MPLL_LOCK, MPLL_CON0, "fout_mpll", NULL),
|
||||
[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
|
||||
BPLL_CON0, NULL),
|
||||
[gpll] = PLL(pll_35xx, fout_gpll, "fout_gpll", "fin_pll", GPLL_LOCK,
|
||||
[gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
|
||||
GPLL_CON0, NULL),
|
||||
[cpll] = PLL(pll_35xx, fout_cpll, "fout_cpll", "fin_pll", CPLL_LOCK,
|
||||
[cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
|
||||
CPLL_CON0, NULL),
|
||||
[epll] = PLL(pll_36xx, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK,
|
||||
[epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
|
||||
EPLL_CON0, NULL),
|
||||
[vpll] = PLL(pll_36xx, fout_vpll, "fout_vpll", "mout_vpllsrc",
|
||||
[vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
|
||||
VPLL_LOCK, VPLL_CON0, NULL),
|
||||
};
|
||||
|
||||
|
|
@ -552,7 +655,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
|
|||
panic("%s: unable to determine soc\n", __func__);
|
||||
}
|
||||
|
||||
samsung_clk_init(np, reg_base, nr_clks,
|
||||
samsung_clk_init(np, reg_base, CLK_NR_CLKS,
|
||||
exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs),
|
||||
NULL, 0);
|
||||
samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
|
||||
|
|
@ -561,8 +664,10 @@ static void __init exynos5250_clk_init(struct device_node *np)
|
|||
samsung_clk_register_mux(exynos5250_pll_pmux_clks,
|
||||
ARRAY_SIZE(exynos5250_pll_pmux_clks));
|
||||
|
||||
if (_get_rate("fin_pll") == 24 * MHZ)
|
||||
if (_get_rate("fin_pll") == 24 * MHZ) {
|
||||
exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
|
||||
exynos5250_plls[apll].rate_table = apll_24mhz_tbl;
|
||||
}
|
||||
|
||||
if (_get_rate("mout_vpllsrc") == 24 * MHZ)
|
||||
exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
|
||||
|
|
@ -581,6 +686,6 @@ static void __init exynos5250_clk_init(struct device_node *np)
|
|||
ARRAY_SIZE(exynos5250_gate_clks));
|
||||
|
||||
pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
|
||||
_get_rate("armclk"));
|
||||
_get_rate("div_arm2"));
|
||||
}
|
||||
CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
* Common Clock Framework support for Exynos5420 SoC.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/exynos5420.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
|
@ -107,48 +108,6 @@ enum exynos5420_plls {
|
|||
nr_plls /* number of PLLs */
|
||||
};
|
||||
|
||||
enum exynos5420_clks {
|
||||
none,
|
||||
|
||||
/* core clocks */
|
||||
fin_pll, fout_apll, fout_cpll, fout_dpll, fout_epll, fout_rpll,
|
||||
fout_ipll, fout_spll, fout_vpll, fout_mpll, fout_bpll, fout_kpll,
|
||||
|
||||
/* gate for special clocks (sclk) */
|
||||
sclk_uart0 = 128, sclk_uart1, sclk_uart2, sclk_uart3, sclk_mmc0,
|
||||
sclk_mmc1, sclk_mmc2, sclk_spi0, sclk_spi1, sclk_spi2, sclk_i2s1,
|
||||
sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel,
|
||||
sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0,
|
||||
sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro,
|
||||
sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, sclk_hdmiphy,
|
||||
|
||||
/* gate clocks */
|
||||
aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
|
||||
i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, spi0, spi1, spi2, keyif, i2s1,
|
||||
i2s2, pcm1, pcm2, pwm, spdif, i2c8, i2c9, i2c10, aclk66_psgen = 300,
|
||||
chipid, sysreg, tzpc0, tzpc1, tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7,
|
||||
tzpc8, tzpc9, hdmi_cec, seckey, mct, wdt, rtc, tmu, tmu_gpu,
|
||||
pclk66_gpio = 330, aclk200_fsys2 = 350, mmc0, mmc1, mmc2, sromc, ufs,
|
||||
aclk200_fsys = 360, tsi, pdma0, pdma1, rtic, usbh20, usbd300, usbd301,
|
||||
aclk400_mscl = 380, mscl0, mscl1, mscl2, smmu_mscl0, smmu_mscl1,
|
||||
smmu_mscl2, aclk333 = 400, mfc, smmu_mfcl, smmu_mfcr,
|
||||
aclk200_disp1 = 410, dsim1, dp1, hdmi, aclk300_disp1 = 420, fimd1,
|
||||
smmu_fimd1, aclk166 = 430, mixer, aclk266 = 440, rotator, mdma1,
|
||||
smmu_rotator, smmu_mdma1, aclk300_jpeg = 450, jpeg, jpeg2, smmu_jpeg,
|
||||
aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0,
|
||||
gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0,
|
||||
aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
|
||||
smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_mixer,
|
||||
|
||||
/* mux clocks */
|
||||
mout_hdmi = 640,
|
||||
|
||||
/* divider clocks */
|
||||
dout_pixel = 768,
|
||||
|
||||
nr_clks,
|
||||
};
|
||||
|
||||
/*
|
||||
* list of controller registers to be saved and restored during a
|
||||
* suspend/resume cycle.
|
||||
|
|
@ -298,225 +257,226 @@ PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
|
|||
|
||||
/* fixed rate clocks generated outside the soc */
|
||||
static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
|
||||
FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
|
||||
FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
|
||||
};
|
||||
|
||||
/* fixed rate clocks generated inside the soc */
|
||||
static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
|
||||
FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
|
||||
FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
|
||||
FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
|
||||
FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
|
||||
FRATE(none, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
|
||||
FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
|
||||
FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
|
||||
FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
|
||||
FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
|
||||
FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
|
||||
};
|
||||
|
||||
static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
|
||||
FFACTOR(none, "sclk_hsic_12m", "fin_pll", 1, 2, 0),
|
||||
FFACTOR(0, "sclk_hsic_12m", "fin_pll", 1, 2, 0),
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
|
||||
MUX(none, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2),
|
||||
MUX(none, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2),
|
||||
MUX(none, "mout_apll", apll_p, SRC_CPU, 0, 1),
|
||||
MUX(none, "mout_cpu", cpu_p, SRC_CPU, 16, 1),
|
||||
MUX(none, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
|
||||
MUX(none, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1),
|
||||
MUX(0, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2),
|
||||
MUX(0, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2),
|
||||
MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
|
||||
MUX(0, "mout_cpu", cpu_p, SRC_CPU, 16, 1),
|
||||
MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
|
||||
MUX(0, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1),
|
||||
|
||||
MUX(none, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
|
||||
MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
|
||||
|
||||
MUX_A(none, "mout_aclk400_mscl", group1_p,
|
||||
MUX_A(0, "mout_aclk400_mscl", group1_p,
|
||||
SRC_TOP0, 4, 2, "aclk400_mscl"),
|
||||
MUX(none, "mout_aclk200", group1_p, SRC_TOP0, 8, 2),
|
||||
MUX(none, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2),
|
||||
MUX(none, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2),
|
||||
MUX(0, "mout_aclk200", group1_p, SRC_TOP0, 8, 2),
|
||||
MUX(0, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2),
|
||||
MUX(0, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2),
|
||||
|
||||
MUX(none, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2),
|
||||
MUX(none, "mout_aclk66", group1_p, SRC_TOP1, 8, 2),
|
||||
MUX(none, "mout_aclk266", group1_p, SRC_TOP1, 20, 2),
|
||||
MUX(none, "mout_aclk166", group1_p, SRC_TOP1, 24, 2),
|
||||
MUX(none, "mout_aclk333", group1_p, SRC_TOP1, 28, 2),
|
||||
MUX(0, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2),
|
||||
MUX(0, "mout_aclk66", group1_p, SRC_TOP1, 8, 2),
|
||||
MUX(0, "mout_aclk266", group1_p, SRC_TOP1, 20, 2),
|
||||
MUX(0, "mout_aclk166", group1_p, SRC_TOP1, 24, 2),
|
||||
MUX(0, "mout_aclk333", group1_p, SRC_TOP1, 28, 2),
|
||||
|
||||
MUX(none, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2),
|
||||
MUX(none, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2),
|
||||
MUX(none, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1),
|
||||
MUX(none, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2),
|
||||
MUX(none, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2),
|
||||
MUX(none, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2),
|
||||
MUX(0, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2),
|
||||
MUX(0, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2),
|
||||
MUX(0, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1),
|
||||
MUX(0, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2),
|
||||
MUX(0, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2),
|
||||
MUX(0, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2),
|
||||
|
||||
MUX(none, "mout_user_aclk400_mscl", user_aclk400_mscl_p,
|
||||
MUX(0, "mout_user_aclk400_mscl", user_aclk400_mscl_p,
|
||||
SRC_TOP3, 4, 1),
|
||||
MUX_A(none, "mout_aclk200_disp1", aclk200_disp1_p,
|
||||
MUX_A(0, "mout_aclk200_disp1", aclk200_disp1_p,
|
||||
SRC_TOP3, 8, 1, "aclk200_disp1"),
|
||||
MUX(none, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p,
|
||||
MUX(0, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p,
|
||||
SRC_TOP3, 12, 1),
|
||||
MUX(none, "mout_user_aclk200_fsys", user_aclk200_fsys_p,
|
||||
MUX(0, "mout_user_aclk200_fsys", user_aclk200_fsys_p,
|
||||
SRC_TOP3, 28, 1),
|
||||
|
||||
MUX(none, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p,
|
||||
MUX(0, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p,
|
||||
SRC_TOP4, 0, 1),
|
||||
MUX(none, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1),
|
||||
MUX(none, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1),
|
||||
MUX(none, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1),
|
||||
MUX(none, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1),
|
||||
MUX(0, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1),
|
||||
MUX(0, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1),
|
||||
MUX(0, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1),
|
||||
MUX(0, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1),
|
||||
|
||||
MUX(none, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1),
|
||||
MUX(none, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1),
|
||||
MUX(none, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1),
|
||||
MUX_A(none, "mout_user_aclk_g3d", user_aclk_g3d_p,
|
||||
MUX(0, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1),
|
||||
MUX(0, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1),
|
||||
MUX(0, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1),
|
||||
MUX_A(0, "mout_user_aclk_g3d", user_aclk_g3d_p,
|
||||
SRC_TOP5, 16, 1, "aclkg3d"),
|
||||
MUX(none, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p,
|
||||
MUX(0, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p,
|
||||
SRC_TOP5, 20, 1),
|
||||
MUX(none, "mout_user_aclk300_disp1", user_aclk300_disp1_p,
|
||||
MUX(0, "mout_user_aclk300_disp1", user_aclk300_disp1_p,
|
||||
SRC_TOP5, 24, 1),
|
||||
MUX(none, "mout_user_aclk300_gscl", user_aclk300_gscl_p,
|
||||
MUX(0, "mout_user_aclk300_gscl", user_aclk300_gscl_p,
|
||||
SRC_TOP5, 28, 1),
|
||||
|
||||
MUX(none, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1),
|
||||
MUX(none, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),
|
||||
MUX(none, "sclk_spll", spll_p, SRC_TOP6, 8, 1),
|
||||
MUX(none, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1),
|
||||
MUX(none, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1),
|
||||
MUX(none, "sclk_epll", epll_p, SRC_TOP6, 20, 1),
|
||||
MUX(none, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1),
|
||||
MUX(none, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1),
|
||||
MUX(0, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1),
|
||||
MUX(0, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),
|
||||
MUX(0, "sclk_spll", spll_p, SRC_TOP6, 8, 1),
|
||||
MUX(0, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1),
|
||||
MUX(0, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1),
|
||||
MUX(0, "sclk_epll", epll_p, SRC_TOP6, 20, 1),
|
||||
MUX(0, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1),
|
||||
MUX(0, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1),
|
||||
|
||||
MUX(none, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
|
||||
MUX(none, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1),
|
||||
MUX(none, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p,
|
||||
MUX(0, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
|
||||
MUX(0, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1),
|
||||
MUX(0, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p,
|
||||
SRC_TOP10, 12, 1),
|
||||
MUX(none, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1),
|
||||
MUX(0, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1),
|
||||
|
||||
MUX(none, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p,
|
||||
MUX(0, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p,
|
||||
SRC_TOP11, 0, 1),
|
||||
MUX(none, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1),
|
||||
MUX(none, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1),
|
||||
MUX(none, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1),
|
||||
MUX(none, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1),
|
||||
MUX(0, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1),
|
||||
MUX(0, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1),
|
||||
MUX(0, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1),
|
||||
MUX(0, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1),
|
||||
|
||||
MUX(none, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1),
|
||||
MUX(none, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1),
|
||||
MUX(none, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1),
|
||||
MUX(none, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1),
|
||||
MUX(none, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p,
|
||||
MUX(0, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1),
|
||||
MUX(0, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1),
|
||||
MUX(0, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1),
|
||||
MUX(0, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1),
|
||||
MUX(0, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p,
|
||||
SRC_TOP12, 24, 1),
|
||||
MUX(none, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
|
||||
MUX(0, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
|
||||
|
||||
/* DISP1 Block */
|
||||
MUX(none, "mout_fimd1", group3_p, SRC_DISP10, 4, 1),
|
||||
MUX(none, "mout_mipi1", group2_p, SRC_DISP10, 16, 3),
|
||||
MUX(none, "mout_dp1", group2_p, SRC_DISP10, 20, 3),
|
||||
MUX(none, "mout_pixel", group2_p, SRC_DISP10, 24, 3),
|
||||
MUX(mout_hdmi, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
|
||||
MUX(0, "mout_fimd1", group3_p, SRC_DISP10, 4, 1),
|
||||
MUX(0, "mout_mipi1", group2_p, SRC_DISP10, 16, 3),
|
||||
MUX(0, "mout_dp1", group2_p, SRC_DISP10, 20, 3),
|
||||
MUX(0, "mout_pixel", group2_p, SRC_DISP10, 24, 3),
|
||||
MUX(CLK_MOUT_HDMI, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
|
||||
|
||||
/* MAU Block */
|
||||
MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
|
||||
MUX(0, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
|
||||
|
||||
/* FSYS Block */
|
||||
MUX(none, "mout_usbd301", group2_p, SRC_FSYS, 4, 3),
|
||||
MUX(none, "mout_mmc0", group2_p, SRC_FSYS, 8, 3),
|
||||
MUX(none, "mout_mmc1", group2_p, SRC_FSYS, 12, 3),
|
||||
MUX(none, "mout_mmc2", group2_p, SRC_FSYS, 16, 3),
|
||||
MUX(none, "mout_usbd300", group2_p, SRC_FSYS, 20, 3),
|
||||
MUX(none, "mout_unipro", group2_p, SRC_FSYS, 24, 3),
|
||||
MUX(0, "mout_usbd301", group2_p, SRC_FSYS, 4, 3),
|
||||
MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 8, 3),
|
||||
MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 12, 3),
|
||||
MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 16, 3),
|
||||
MUX(0, "mout_usbd300", group2_p, SRC_FSYS, 20, 3),
|
||||
MUX(0, "mout_unipro", group2_p, SRC_FSYS, 24, 3),
|
||||
|
||||
/* PERIC Block */
|
||||
MUX(none, "mout_uart0", group2_p, SRC_PERIC0, 4, 3),
|
||||
MUX(none, "mout_uart1", group2_p, SRC_PERIC0, 8, 3),
|
||||
MUX(none, "mout_uart2", group2_p, SRC_PERIC0, 12, 3),
|
||||
MUX(none, "mout_uart3", group2_p, SRC_PERIC0, 16, 3),
|
||||
MUX(none, "mout_pwm", group2_p, SRC_PERIC0, 24, 3),
|
||||
MUX(none, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3),
|
||||
MUX(none, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3),
|
||||
MUX(none, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3),
|
||||
MUX(none, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3),
|
||||
MUX(none, "mout_spi0", group2_p, SRC_PERIC1, 20, 3),
|
||||
MUX(none, "mout_spi1", group2_p, SRC_PERIC1, 24, 3),
|
||||
MUX(none, "mout_spi2", group2_p, SRC_PERIC1, 28, 3),
|
||||
MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 4, 3),
|
||||
MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 8, 3),
|
||||
MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 12, 3),
|
||||
MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 16, 3),
|
||||
MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 3),
|
||||
MUX(0, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3),
|
||||
MUX(0, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3),
|
||||
MUX(0, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3),
|
||||
MUX(0, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3),
|
||||
MUX(0, "mout_spi0", group2_p, SRC_PERIC1, 20, 3),
|
||||
MUX(0, "mout_spi1", group2_p, SRC_PERIC1, 24, 3),
|
||||
MUX(0, "mout_spi2", group2_p, SRC_PERIC1, 28, 3),
|
||||
};
|
||||
|
||||
static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
|
||||
DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
|
||||
DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
|
||||
DIV(none, "armclk2", "div_arm", DIV_CPU0, 28, 3),
|
||||
DIV(none, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3),
|
||||
DIV(none, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
|
||||
DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
|
||||
DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
|
||||
DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
|
||||
DIV(0, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3),
|
||||
DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
|
||||
|
||||
DIV(none, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
|
||||
DIV(none, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
|
||||
DIV(none, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
|
||||
DIV(none, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
|
||||
DIV(none, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
|
||||
DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
|
||||
DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
|
||||
DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
|
||||
DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
|
||||
DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
|
||||
|
||||
DIV(none, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
|
||||
DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
|
||||
DIV_TOP1, 0, 3),
|
||||
DIV(none, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
|
||||
DIV(none, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
|
||||
DIV(none, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
|
||||
DIV(none, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
|
||||
DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
|
||||
DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
|
||||
DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
|
||||
DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
|
||||
|
||||
DIV(none, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
|
||||
DIV(none, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
|
||||
DIV(none, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
|
||||
DIV(none, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
|
||||
DIV_A(none, "dout_aclk300_disp1", "mout_aclk300_disp1",
|
||||
DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
|
||||
DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
|
||||
DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
|
||||
DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
|
||||
DIV_A(0, "dout_aclk300_disp1", "mout_aclk300_disp1",
|
||||
DIV_TOP2, 24, 3, "aclk300_disp1"),
|
||||
DIV(none, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
|
||||
DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
|
||||
|
||||
/* DISP1 Block */
|
||||
DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
|
||||
DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
|
||||
DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
|
||||
DIV(dout_pixel, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
|
||||
DIV(0, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
|
||||
DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
|
||||
DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
|
||||
DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
|
||||
|
||||
/* Audio Block */
|
||||
DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
|
||||
DIV(none, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
|
||||
DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
|
||||
DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
|
||||
|
||||
/* USB3.0 */
|
||||
DIV(none, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
|
||||
DIV(none, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
|
||||
DIV(none, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
|
||||
DIV(none, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
|
||||
DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
|
||||
DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
|
||||
DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
|
||||
DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
|
||||
|
||||
/* MMC */
|
||||
DIV(none, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
|
||||
DIV(none, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
|
||||
DIV(none, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
|
||||
DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
|
||||
DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
|
||||
DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
|
||||
|
||||
DIV(none, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
|
||||
DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
|
||||
|
||||
/* UART and PWM */
|
||||
DIV(none, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
|
||||
DIV(none, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
|
||||
DIV(none, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
|
||||
DIV(none, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
|
||||
DIV(none, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
|
||||
DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
|
||||
DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
|
||||
DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
|
||||
DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
|
||||
DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
|
||||
|
||||
/* SPI */
|
||||
DIV(none, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
|
||||
DIV(none, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
|
||||
DIV(none, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
|
||||
DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
|
||||
DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
|
||||
DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
|
||||
|
||||
/* PCM */
|
||||
DIV(none, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
|
||||
DIV(none, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
|
||||
DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
|
||||
DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
|
||||
|
||||
/* Audio - I2S */
|
||||
DIV(none, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
|
||||
DIV(none, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
|
||||
DIV(none, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
|
||||
DIV(none, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
|
||||
DIV(none, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
|
||||
DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
|
||||
DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
|
||||
DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
|
||||
DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
|
||||
DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
|
||||
|
||||
/* SPI Pre-Ratio */
|
||||
DIV(none, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8),
|
||||
DIV(none, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8),
|
||||
DIV(none, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8),
|
||||
DIV(0, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8),
|
||||
DIV(0, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8),
|
||||
DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
|
||||
/* TODO: Re-verify the CG bits for all the gate clocks */
|
||||
GATE_A(mct, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, "mct"),
|
||||
GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0,
|
||||
"mct"),
|
||||
|
||||
GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
|
||||
GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
|
||||
|
|
@ -545,217 +505,227 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
|
|||
GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
|
||||
|
||||
/* sclk */
|
||||
GATE(sclk_uart0, "sclk_uart0", "dout_uart0",
|
||||
GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
|
||||
GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_uart1, "sclk_uart1", "dout_uart1",
|
||||
GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
|
||||
GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_uart2, "sclk_uart2", "dout_uart2",
|
||||
GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
|
||||
GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_uart3, "sclk_uart3", "dout_uart3",
|
||||
GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
|
||||
GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_spi0, "sclk_spi0", "dout_pre_spi0",
|
||||
GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_pre_spi0",
|
||||
GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_spi1, "sclk_spi1", "dout_pre_spi1",
|
||||
GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_pre_spi1",
|
||||
GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_spi2, "sclk_spi2", "dout_pre_spi2",
|
||||
GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_pre_spi2",
|
||||
GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
|
||||
GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
|
||||
GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_pwm, "sclk_pwm", "dout_pwm",
|
||||
GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
|
||||
GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_pcm1, "sclk_pcm1", "dout_pcm1",
|
||||
GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
|
||||
GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_pcm2, "sclk_pcm2", "dout_pcm2",
|
||||
GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
|
||||
GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_i2s1, "sclk_i2s1", "dout_i2s1",
|
||||
GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
|
||||
GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_i2s2, "sclk_i2s2", "dout_i2s2",
|
||||
GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
|
||||
GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
|
||||
|
||||
GATE(sclk_mmc0, "sclk_mmc0", "dout_mmc0",
|
||||
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
|
||||
GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_mmc1, "sclk_mmc1", "dout_mmc1",
|
||||
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
|
||||
GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_mmc2, "sclk_mmc2", "dout_mmc2",
|
||||
GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
|
||||
GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_usbphy301, "sclk_usbphy301", "dout_usbphy301",
|
||||
GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
|
||||
GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_usbphy300, "sclk_usbphy300", "dout_usbphy300",
|
||||
GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
|
||||
GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_usbd300, "sclk_usbd300", "dout_usbd300",
|
||||
GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
|
||||
GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_usbd301, "sclk_usbd301", "dout_usbd301",
|
||||
GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
|
||||
GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
|
||||
|
||||
GATE(sclk_usbd301, "sclk_unipro", "dout_unipro",
|
||||
GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro",
|
||||
SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
|
||||
|
||||
GATE(sclk_gscl_wa, "sclk_gscl_wa", "aclK333_432_gscl",
|
||||
GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "aclK333_432_gscl",
|
||||
GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_gscl_wb, "sclk_gscl_wb", "aclk333_432_gscl",
|
||||
GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "aclk333_432_gscl",
|
||||
GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0),
|
||||
|
||||
/* Display */
|
||||
GATE(sclk_fimd1, "sclk_fimd1", "dout_fimd1",
|
||||
GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
|
||||
GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_mipi1, "sclk_mipi1", "dout_mipi1",
|
||||
GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
|
||||
GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
|
||||
GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
|
||||
GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel",
|
||||
GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
|
||||
GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_dp1, "sclk_dp1", "dout_dp1",
|
||||
GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
|
||||
GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
|
||||
|
||||
/* Maudio Block */
|
||||
GATE(sclk_maudio0, "sclk_maudio0", "dout_maudio0",
|
||||
GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
|
||||
GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(sclk_maupcm0, "sclk_maupcm0", "dout_maupcm0",
|
||||
GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
|
||||
GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
|
||||
/* FSYS */
|
||||
GATE(tsi, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
|
||||
GATE(pdma0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
|
||||
GATE(pdma1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
|
||||
GATE(ufs, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
|
||||
GATE(rtic, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
|
||||
GATE(mmc0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
|
||||
GATE(mmc1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
|
||||
GATE(mmc2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
|
||||
GATE(sromc, "sromc", "aclk200_fsys2",
|
||||
GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
|
||||
GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
|
||||
GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
|
||||
GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
|
||||
GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
|
||||
GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
|
||||
GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
|
||||
GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
|
||||
GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
|
||||
GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(usbh20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0),
|
||||
GATE(usbd300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0),
|
||||
GATE(usbd301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0),
|
||||
GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0),
|
||||
GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0),
|
||||
GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0),
|
||||
|
||||
/* UART */
|
||||
GATE(uart0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
|
||||
GATE(uart1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
|
||||
GATE_A(uart2, "uart2", "aclk66_peric",
|
||||
GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
|
||||
GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
|
||||
GATE_A(CLK_UART2, "uart2", "aclk66_peric",
|
||||
GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
|
||||
GATE(uart3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
|
||||
GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
|
||||
/* I2C */
|
||||
GATE(i2c0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
|
||||
GATE(i2c1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
|
||||
GATE(i2c2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
|
||||
GATE(i2c3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
|
||||
GATE(i2c4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
|
||||
GATE(i2c5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
|
||||
GATE(i2c6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
|
||||
GATE(i2c7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
|
||||
GATE(i2c_hdmi, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0, 0),
|
||||
GATE(tsadc, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
|
||||
GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
|
||||
GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
|
||||
GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
|
||||
GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
|
||||
GATE(CLK_I2C4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
|
||||
GATE(CLK_I2C5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
|
||||
GATE(CLK_I2C6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
|
||||
GATE(CLK_I2C7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
|
||||
GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0,
|
||||
0),
|
||||
GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
|
||||
/* SPI */
|
||||
GATE(spi0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
|
||||
GATE(spi1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
|
||||
GATE(spi2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
|
||||
GATE(keyif, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
|
||||
GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
|
||||
GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
|
||||
GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
|
||||
GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
|
||||
/* I2S */
|
||||
GATE(i2s1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
|
||||
GATE(i2s2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
|
||||
GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
|
||||
GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
|
||||
/* PCM */
|
||||
GATE(pcm1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
|
||||
GATE(pcm2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
|
||||
GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
|
||||
GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
|
||||
/* PWM */
|
||||
GATE(pwm, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
|
||||
GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
|
||||
/* SPDIF */
|
||||
GATE(spdif, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
|
||||
GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
|
||||
|
||||
GATE(i2c8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0),
|
||||
GATE(i2c9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0),
|
||||
GATE(i2c10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0),
|
||||
GATE(CLK_I2C8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0),
|
||||
GATE(CLK_I2C9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0),
|
||||
GATE(CLK_I2C10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0),
|
||||
|
||||
GATE(chipid, "chipid", "aclk66_psgen",
|
||||
GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
|
||||
GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(sysreg, "sysreg", "aclk66_psgen",
|
||||
GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
|
||||
GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(tzpc0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0),
|
||||
GATE(tzpc1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0),
|
||||
GATE(tzpc2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0),
|
||||
GATE(tzpc3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0),
|
||||
GATE(tzpc4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0),
|
||||
GATE(tzpc5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0),
|
||||
GATE(tzpc6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0),
|
||||
GATE(tzpc7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0),
|
||||
GATE(tzpc8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0),
|
||||
GATE(tzpc9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0),
|
||||
GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0),
|
||||
GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0),
|
||||
GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0),
|
||||
GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0),
|
||||
GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0),
|
||||
GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0),
|
||||
GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0),
|
||||
GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0),
|
||||
GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0),
|
||||
GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0),
|
||||
|
||||
GATE(hdmi_cec, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 0),
|
||||
GATE(seckey, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
|
||||
GATE(wdt, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
|
||||
GATE(rtc, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
|
||||
GATE(tmu, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
|
||||
GATE(tmu_gpu, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0),
|
||||
GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0,
|
||||
0),
|
||||
GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
|
||||
GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
|
||||
GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
|
||||
GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
|
||||
GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0),
|
||||
|
||||
GATE(gscl0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
|
||||
GATE(gscl1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
|
||||
GATE(clk_3aa, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0),
|
||||
GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
|
||||
GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
|
||||
GATE(CLK_CLK_3AA, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0),
|
||||
|
||||
GATE(smmu_3aa, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0, 0),
|
||||
GATE(smmu_fimcl0, "smmu_fimcl0", "aclk333_432_gscl",
|
||||
GATE(CLK_SMMU_3AA, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0,
|
||||
0),
|
||||
GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "aclk333_432_gscl",
|
||||
GATE_IP_GSCL1, 3, 0, 0),
|
||||
GATE(smmu_fimcl1, "smmu_fimcl1", "aclk333_432_gscl",
|
||||
GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "aclk333_432_gscl",
|
||||
GATE_IP_GSCL1, 4, 0, 0),
|
||||
GATE(smmu_gscl0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0, 0),
|
||||
GATE(smmu_gscl1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0, 0),
|
||||
GATE(gscl_wa, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0),
|
||||
GATE(gscl_wb, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0),
|
||||
GATE(smmu_fimcl3, "smmu_fimcl3,", "aclk333_432_gscl",
|
||||
GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0,
|
||||
0),
|
||||
GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0,
|
||||
0),
|
||||
GATE(CLK_GSCL_WA, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0),
|
||||
GATE(CLK_GSCL_WB, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0),
|
||||
GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "aclk333_432_gscl",
|
||||
GATE_IP_GSCL1, 16, 0, 0),
|
||||
GATE(fimc_lite3, "fimc_lite3", "aclk333_432_gscl",
|
||||
GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
|
||||
GATE_IP_GSCL1, 17, 0, 0),
|
||||
|
||||
GATE(fimd1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
|
||||
GATE(dsim1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
|
||||
GATE(dp1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
|
||||
GATE(mixer, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
|
||||
GATE(hdmi, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
|
||||
GATE(smmu_fimd1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 0),
|
||||
GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
|
||||
GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
|
||||
GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
|
||||
GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
|
||||
GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
|
||||
GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0,
|
||||
0),
|
||||
|
||||
GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
|
||||
GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
|
||||
GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
|
||||
GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
|
||||
GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
|
||||
GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
|
||||
|
||||
GATE(g3d, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
|
||||
GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
|
||||
|
||||
GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
|
||||
GATE(jpeg, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
|
||||
GATE(jpeg2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
|
||||
GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
|
||||
GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
|
||||
GATE(smmu_jpeg, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
|
||||
GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
|
||||
GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
|
||||
GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
|
||||
GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
|
||||
GATE(CLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
|
||||
GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
|
||||
GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
|
||||
GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
|
||||
|
||||
GATE(mscl0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
|
||||
GATE(mscl1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
|
||||
GATE(mscl2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
|
||||
GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0),
|
||||
GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0),
|
||||
GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0),
|
||||
GATE(smmu_mixer, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 0),
|
||||
GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
|
||||
GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
|
||||
GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
|
||||
GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0,
|
||||
0),
|
||||
GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0,
|
||||
0),
|
||||
GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0,
|
||||
0),
|
||||
GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
|
||||
0),
|
||||
};
|
||||
|
||||
static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
|
||||
[apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
|
||||
[apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
|
||||
APLL_CON0, NULL),
|
||||
[cpll] = PLL(pll_2550, fout_cpll, "fout_cpll", "fin_pll", CPLL_LOCK,
|
||||
[cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
|
||||
CPLL_CON0, NULL),
|
||||
[dpll] = PLL(pll_2550, fout_dpll, "fout_dpll", "fin_pll", DPLL_LOCK,
|
||||
[dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
|
||||
DPLL_CON0, NULL),
|
||||
[epll] = PLL(pll_2650, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK,
|
||||
[epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
|
||||
EPLL_CON0, NULL),
|
||||
[rpll] = PLL(pll_2650, fout_rpll, "fout_rpll", "fin_pll", RPLL_LOCK,
|
||||
[rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
|
||||
RPLL_CON0, NULL),
|
||||
[ipll] = PLL(pll_2550, fout_ipll, "fout_ipll", "fin_pll", IPLL_LOCK,
|
||||
[ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
|
||||
IPLL_CON0, NULL),
|
||||
[spll] = PLL(pll_2550, fout_spll, "fout_spll", "fin_pll", SPLL_LOCK,
|
||||
[spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
|
||||
SPLL_CON0, NULL),
|
||||
[vpll] = PLL(pll_2550, fout_vpll, "fout_vpll", "fin_pll", VPLL_LOCK,
|
||||
[vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
|
||||
VPLL_CON0, NULL),
|
||||
[mpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK,
|
||||
[mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
|
||||
MPLL_CON0, NULL),
|
||||
[bpll] = PLL(pll_2550, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK,
|
||||
[bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
|
||||
BPLL_CON0, NULL),
|
||||
[kpll] = PLL(pll_2550, fout_kpll, "fout_kpll", "fin_pll", KPLL_LOCK,
|
||||
[kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
|
||||
KPLL_CON0, NULL),
|
||||
};
|
||||
|
||||
|
|
@ -777,7 +747,7 @@ static void __init exynos5420_clk_init(struct device_node *np)
|
|||
panic("%s: unable to determine soc\n", __func__);
|
||||
}
|
||||
|
||||
samsung_clk_init(np, reg_base, nr_clks,
|
||||
samsung_clk_init(np, reg_base, CLK_NR_CLKS,
|
||||
exynos5420_clk_regs, ARRAY_SIZE(exynos5420_clk_regs),
|
||||
NULL, 0);
|
||||
samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
* Common Clock Framework support for Exynos5440 SoC.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/exynos5440.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
|
@ -22,79 +23,65 @@
|
|||
#define CPU_CLK_STATUS 0xfc
|
||||
#define MISC_DOUT1 0x558
|
||||
|
||||
/*
|
||||
* Let each supported clock get a unique id. This id is used to lookup the clock
|
||||
* for device tree based platforms.
|
||||
*/
|
||||
enum exynos5440_clks {
|
||||
none, xtal, arm_clk,
|
||||
|
||||
spi_baud = 16, pb0_250, pr0_250, pr1_250, b_250, b_125, b_200, sata,
|
||||
usb, gmac0, cs250, pb0_250_o, pr0_250_o, pr1_250_o, b_250_o, b_125_o,
|
||||
b_200_o, sata_o, usb_o, gmac0_o, cs250_o,
|
||||
|
||||
nr_clks,
|
||||
};
|
||||
|
||||
/* parent clock name list */
|
||||
PNAME(mout_armclk_p) = { "cplla", "cpllb" };
|
||||
PNAME(mout_spi_p) = { "div125", "div200" };
|
||||
|
||||
/* fixed rate clocks generated outside the soc */
|
||||
static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
|
||||
FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0),
|
||||
FRATE(0, "xtal", NULL, CLK_IS_ROOT, 0),
|
||||
};
|
||||
|
||||
/* fixed rate clocks */
|
||||
static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
|
||||
FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000),
|
||||
FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000),
|
||||
FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000),
|
||||
FRATE(none, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000),
|
||||
FRATE(none, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000),
|
||||
FRATE(0, "ppll", NULL, CLK_IS_ROOT, 1000000000),
|
||||
FRATE(0, "usb_phy0", NULL, CLK_IS_ROOT, 60000000),
|
||||
FRATE(0, "usb_phy1", NULL, CLK_IS_ROOT, 60000000),
|
||||
FRATE(0, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000),
|
||||
FRATE(0, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000),
|
||||
};
|
||||
|
||||
/* fixed factor clocks */
|
||||
static struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
|
||||
FFACTOR(none, "div250", "ppll", 1, 4, 0),
|
||||
FFACTOR(none, "div200", "ppll", 1, 5, 0),
|
||||
FFACTOR(none, "div125", "div250", 1, 2, 0),
|
||||
FFACTOR(0, "div250", "ppll", 1, 4, 0),
|
||||
FFACTOR(0, "div200", "ppll", 1, 5, 0),
|
||||
FFACTOR(0, "div125", "div250", 1, 2, 0),
|
||||
};
|
||||
|
||||
/* mux clocks */
|
||||
static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
|
||||
MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
|
||||
MUX_A(arm_clk, "arm_clk", mout_armclk_p,
|
||||
MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
|
||||
MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p,
|
||||
CPU_CLK_STATUS, 0, 1, "armclk"),
|
||||
};
|
||||
|
||||
/* divider clocks */
|
||||
static struct samsung_div_clock exynos5440_div_clks[] __initdata = {
|
||||
DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
|
||||
DIV(CLK_SPI_BAUD, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
|
||||
};
|
||||
|
||||
/* gate clocks */
|
||||
static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
|
||||
GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
|
||||
GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
|
||||
GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
|
||||
GATE(b_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
|
||||
GATE(b_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
|
||||
GATE(b_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
|
||||
GATE(sata, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
|
||||
GATE(usb, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
|
||||
GATE(gmac0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
|
||||
GATE(cs250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
|
||||
GATE(pb0_250_o, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
|
||||
GATE(pr0_250_o, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
|
||||
GATE(pr1_250_o, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
|
||||
GATE(b_250_o, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
|
||||
GATE(b_125_o, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
|
||||
GATE(b_200_o, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
|
||||
GATE(sata_o, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
|
||||
GATE(usb_o, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
|
||||
GATE(gmac0_o, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
|
||||
GATE(cs250_o, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
|
||||
GATE(CLK_PB0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
|
||||
GATE(CLK_PR0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
|
||||
GATE(CLK_PR1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
|
||||
GATE(CLK_B_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
|
||||
GATE(CLK_B_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
|
||||
GATE(CLK_B_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
|
||||
GATE(CLK_SATA, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
|
||||
GATE(CLK_USB, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
|
||||
GATE(CLK_GMAC0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
|
||||
GATE(CLK_CS250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
|
||||
GATE(CLK_PB0_250_O, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
|
||||
GATE(CLK_PR0_250_O, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
|
||||
GATE(CLK_PR1_250_O, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
|
||||
GATE(CLK_B_250_O, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
|
||||
GATE(CLK_B_125_O, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
|
||||
GATE(CLK_B_200_O, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
|
||||
GATE(CLK_SATA_O, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
|
||||
GATE(CLK_USB_O, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
|
||||
GATE(CLK_GMAC0_O, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
|
||||
GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
|
||||
};
|
||||
|
||||
static struct of_device_id ext_clk_match[] __initdata = {
|
||||
|
|
@ -114,7 +101,7 @@ static void __init exynos5440_clk_init(struct device_node *np)
|
|||
return;
|
||||
}
|
||||
|
||||
samsung_clk_init(np, reg_base, nr_clks, NULL, 0, NULL, 0);
|
||||
samsung_clk_init(np, reg_base, CLK_NR_CLKS, NULL, 0, NULL, 0);
|
||||
samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
|
||||
ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
|
||||
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@
|
|||
#define EXYNOS_SCLK_I2S 7
|
||||
#define EXYNOS_PCM_BUS 8
|
||||
#define EXYNOS_SCLK_PCM 9
|
||||
#define EXYNOS_ADMA 10
|
||||
|
||||
#define EXYNOS_AUDSS_MAX_CLKS 10
|
||||
#define EXYNOS_AUDSS_MAX_CLKS 11
|
||||
|
||||
#endif
|
||||
|
|
|
|||
244
include/dt-bindings/clock/exynos4.h
Normal file
244
include/dt-bindings/clock/exynos4.h
Normal file
|
|
@ -0,0 +1,244 @@
|
|||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* Author: Andrzej Haja <a.hajda@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Device Tree binding constants for Exynos4 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS_4_H
|
||||
|
||||
/* core clocks */
|
||||
#define CLK_XXTI 1
|
||||
#define CLK_XUSBXTI 2
|
||||
#define CLK_FIN_PLL 3
|
||||
#define CLK_FOUT_APLL 4
|
||||
#define CLK_FOUT_MPLL 5
|
||||
#define CLK_FOUT_EPLL 6
|
||||
#define CLK_FOUT_VPLL 7
|
||||
#define CLK_SCLK_APLL 8
|
||||
#define CLK_SCLK_MPLL 9
|
||||
#define CLK_SCLK_EPLL 10
|
||||
#define CLK_SCLK_VPLL 11
|
||||
#define CLK_ARM_CLK 12
|
||||
#define CLK_ACLK200 13
|
||||
#define CLK_ACLK100 14
|
||||
#define CLK_ACLK160 15
|
||||
#define CLK_ACLK133 16
|
||||
#define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */
|
||||
#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
|
||||
#define CLK_MOUT_CORE 19
|
||||
#define CLK_MOUT_APLL 20
|
||||
|
||||
/* gate for special clocks (sclk) */
|
||||
#define CLK_SCLK_FIMC0 128
|
||||
#define CLK_SCLK_FIMC1 129
|
||||
#define CLK_SCLK_FIMC2 130
|
||||
#define CLK_SCLK_FIMC3 131
|
||||
#define CLK_SCLK_CAM0 132
|
||||
#define CLK_SCLK_CAM1 133
|
||||
#define CLK_SCLK_CSIS0 134
|
||||
#define CLK_SCLK_CSIS1 135
|
||||
#define CLK_SCLK_HDMI 136
|
||||
#define CLK_SCLK_MIXER 137
|
||||
#define CLK_SCLK_DAC 138
|
||||
#define CLK_SCLK_PIXEL 139
|
||||
#define CLK_SCLK_FIMD0 140
|
||||
#define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */
|
||||
#define CLK_SCLK_MDNIE_PWM0 142
|
||||
#define CLK_SCLK_MIPI0 143
|
||||
#define CLK_SCLK_AUDIO0 144
|
||||
#define CLK_SCLK_MMC0 145
|
||||
#define CLK_SCLK_MMC1 146
|
||||
#define CLK_SCLK_MMC2 147
|
||||
#define CLK_SCLK_MMC3 148
|
||||
#define CLK_SCLK_MMC4 149
|
||||
#define CLK_SCLK_SATA 150 /* Exynos4210 only */
|
||||
#define CLK_SCLK_UART0 151
|
||||
#define CLK_SCLK_UART1 152
|
||||
#define CLK_SCLK_UART2 153
|
||||
#define CLK_SCLK_UART3 154
|
||||
#define CLK_SCLK_UART4 155
|
||||
#define CLK_SCLK_AUDIO1 156
|
||||
#define CLK_SCLK_AUDIO2 157
|
||||
#define CLK_SCLK_SPDIF 158
|
||||
#define CLK_SCLK_SPI0 159
|
||||
#define CLK_SCLK_SPI1 160
|
||||
#define CLK_SCLK_SPI2 161
|
||||
#define CLK_SCLK_SLIMBUS 162
|
||||
#define CLK_SCLK_FIMD1 163 /* Exynos4210 only */
|
||||
#define CLK_SCLK_MIPI1 164 /* Exynos4210 only */
|
||||
#define CLK_SCLK_PCM1 165
|
||||
#define CLK_SCLK_PCM2 166
|
||||
#define CLK_SCLK_I2S1 167
|
||||
#define CLK_SCLK_I2S2 168
|
||||
#define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */
|
||||
#define CLK_SCLK_MFC 170
|
||||
#define CLK_SCLK_PCM0 171
|
||||
#define CLK_SCLK_G3D 172
|
||||
#define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */
|
||||
#define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */
|
||||
#define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */
|
||||
#define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */
|
||||
#define CLK_SCLK_FIMG2D 177
|
||||
|
||||
/* gate clocks */
|
||||
#define CLK_FIMC0 256
|
||||
#define CLK_FIMC1 257
|
||||
#define CLK_FIMC2 258
|
||||
#define CLK_FIMC3 259
|
||||
#define CLK_CSIS0 260
|
||||
#define CLK_CSIS1 261
|
||||
#define CLK_JPEG 262
|
||||
#define CLK_SMMU_FIMC0 263
|
||||
#define CLK_SMMU_FIMC1 264
|
||||
#define CLK_SMMU_FIMC2 265
|
||||
#define CLK_SMMU_FIMC3 266
|
||||
#define CLK_SMMU_JPEG 267
|
||||
#define CLK_VP 268
|
||||
#define CLK_MIXER 269
|
||||
#define CLK_TVENC 270 /* Exynos4210 only */
|
||||
#define CLK_HDMI 271
|
||||
#define CLK_SMMU_TV 272
|
||||
#define CLK_MFC 273
|
||||
#define CLK_SMMU_MFCL 274
|
||||
#define CLK_SMMU_MFCR 275
|
||||
#define CLK_G3D 276
|
||||
#define CLK_G2D 277
|
||||
#define CLK_ROTATOR 278 /* Exynos4210 only */
|
||||
#define CLK_MDMA 279 /* Exynos4210 only */
|
||||
#define CLK_SMMU_G2D 280 /* Exynos4210 only */
|
||||
#define CLK_SMMU_ROTATOR 281 /* Exynos4210 only */
|
||||
#define CLK_SMMU_MDMA 282 /* Exynos4210 only */
|
||||
#define CLK_FIMD0 283
|
||||
#define CLK_MIE0 284
|
||||
#define CLK_MDNIE0 285 /* Exynos4412 only */
|
||||
#define CLK_DSIM0 286
|
||||
#define CLK_SMMU_FIMD0 287
|
||||
#define CLK_FIMD1 288 /* Exynos4210 only */
|
||||
#define CLK_MIE1 289 /* Exynos4210 only */
|
||||
#define CLK_DSIM1 290 /* Exynos4210 only */
|
||||
#define CLK_SMMU_FIMD1 291 /* Exynos4210 only */
|
||||
#define CLK_PDMA0 292
|
||||
#define CLK_PDMA1 293
|
||||
#define CLK_PCIE_PHY 294
|
||||
#define CLK_SATA_PHY 295 /* Exynos4210 only */
|
||||
#define CLK_TSI 296
|
||||
#define CLK_SDMMC0 297
|
||||
#define CLK_SDMMC1 298
|
||||
#define CLK_SDMMC2 299
|
||||
#define CLK_SDMMC3 300
|
||||
#define CLK_SDMMC4 301
|
||||
#define CLK_SATA 302 /* Exynos4210 only */
|
||||
#define CLK_SROMC 303
|
||||
#define CLK_USB_HOST 304
|
||||
#define CLK_USB_DEVICE 305
|
||||
#define CLK_PCIE 306
|
||||
#define CLK_ONENAND 307
|
||||
#define CLK_NFCON 308
|
||||
#define CLK_SMMU_PCIE 309
|
||||
#define CLK_GPS 310
|
||||
#define CLK_SMMU_GPS 311
|
||||
#define CLK_UART0 312
|
||||
#define CLK_UART1 313
|
||||
#define CLK_UART2 314
|
||||
#define CLK_UART3 315
|
||||
#define CLK_UART4 316
|
||||
#define CLK_I2C0 317
|
||||
#define CLK_I2C1 318
|
||||
#define CLK_I2C2 319
|
||||
#define CLK_I2C3 320
|
||||
#define CLK_I2C4 321
|
||||
#define CLK_I2C5 322
|
||||
#define CLK_I2C6 323
|
||||
#define CLK_I2C7 324
|
||||
#define CLK_I2C_HDMI 325
|
||||
#define CLK_TSADC 326
|
||||
#define CLK_SPI0 327
|
||||
#define CLK_SPI1 328
|
||||
#define CLK_SPI2 329
|
||||
#define CLK_I2S1 330
|
||||
#define CLK_I2S2 331
|
||||
#define CLK_PCM0 332
|
||||
#define CLK_I2S0 333
|
||||
#define CLK_PCM1 334
|
||||
#define CLK_PCM2 335
|
||||
#define CLK_PWM 336
|
||||
#define CLK_SLIMBUS 337
|
||||
#define CLK_SPDIF 338
|
||||
#define CLK_AC97 339
|
||||
#define CLK_MODEMIF 340
|
||||
#define CLK_CHIPID 341
|
||||
#define CLK_SYSREG 342
|
||||
#define CLK_HDMI_CEC 343
|
||||
#define CLK_MCT 344
|
||||
#define CLK_WDT 345
|
||||
#define CLK_RTC 346
|
||||
#define CLK_KEYIF 347
|
||||
#define CLK_AUDSS 348
|
||||
#define CLK_MIPI_HSI 349 /* Exynos4210 only */
|
||||
#define CLK_MDMA2 350 /* Exynos4210 only */
|
||||
#define CLK_PIXELASYNCM0 351
|
||||
#define CLK_PIXELASYNCM1 352
|
||||
#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
|
||||
#define CLK_FIMC_LITE1 354 /* Exynos4x12 only */
|
||||
#define CLK_PPMUISPX 355 /* Exynos4x12 only */
|
||||
#define CLK_PPMUISPMX 356 /* Exynos4x12 only */
|
||||
#define CLK_FIMC_ISP 357 /* Exynos4x12 only */
|
||||
#define CLK_FIMC_DRC 358 /* Exynos4x12 only */
|
||||
#define CLK_FIMC_FD 359 /* Exynos4x12 only */
|
||||
#define CLK_MCUISP 360 /* Exynos4x12 only */
|
||||
#define CLK_GICISP 361 /* Exynos4x12 only */
|
||||
#define CLK_SMMU_ISP 362 /* Exynos4x12 only */
|
||||
#define CLK_SMMU_DRC 363 /* Exynos4x12 only */
|
||||
#define CLK_SMMU_FD 364 /* Exynos4x12 only */
|
||||
#define CLK_SMMU_LITE0 365 /* Exynos4x12 only */
|
||||
#define CLK_SMMU_LITE1 366 /* Exynos4x12 only */
|
||||
#define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */
|
||||
#define CLK_MPWM_ISP 368 /* Exynos4x12 only */
|
||||
#define CLK_I2C0_ISP 369 /* Exynos4x12 only */
|
||||
#define CLK_I2C1_ISP 370 /* Exynos4x12 only */
|
||||
#define CLK_MTCADC_ISP 371 /* Exynos4x12 only */
|
||||
#define CLK_PWM_ISP 372 /* Exynos4x12 only */
|
||||
#define CLK_WDT_ISP 373 /* Exynos4x12 only */
|
||||
#define CLK_UART_ISP 374 /* Exynos4x12 only */
|
||||
#define CLK_ASYNCAXIM 375 /* Exynos4x12 only */
|
||||
#define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */
|
||||
#define CLK_SPI0_ISP 377 /* Exynos4x12 only */
|
||||
#define CLK_SPI1_ISP 378 /* Exynos4x12 only */
|
||||
#define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
|
||||
#define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
|
||||
#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
|
||||
#define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */
|
||||
#define CLK_TMU_APBIF 383
|
||||
|
||||
/* mux clocks */
|
||||
#define CLK_MOUT_FIMC0 384
|
||||
#define CLK_MOUT_FIMC1 385
|
||||
#define CLK_MOUT_FIMC2 386
|
||||
#define CLK_MOUT_FIMC3 387
|
||||
#define CLK_MOUT_CAM0 388
|
||||
#define CLK_MOUT_CAM1 389
|
||||
#define CLK_MOUT_CSIS0 390
|
||||
#define CLK_MOUT_CSIS1 391
|
||||
#define CLK_MOUT_G3D0 392
|
||||
#define CLK_MOUT_G3D1 393
|
||||
#define CLK_MOUT_G3D 394
|
||||
#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
|
||||
|
||||
/* div clocks */
|
||||
#define CLK_DIV_ISP0 450 /* Exynos4x12 only */
|
||||
#define CLK_DIV_ISP1 451 /* Exynos4x12 only */
|
||||
#define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */
|
||||
#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
|
||||
#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
|
||||
#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
|
||||
|
||||
/* must be greater than maximal clock id */
|
||||
#define CLK_NR_CLKS 456
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
|
||||
160
include/dt-bindings/clock/exynos5250.h
Normal file
160
include/dt-bindings/clock/exynos5250.h
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* Author: Andrzej Haja <a.hajda@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Device Tree binding constants for Exynos5250 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H
|
||||
|
||||
/* core clocks */
|
||||
#define CLK_FIN_PLL 1
|
||||
#define CLK_FOUT_APLL 2
|
||||
#define CLK_FOUT_MPLL 3
|
||||
#define CLK_FOUT_BPLL 4
|
||||
#define CLK_FOUT_GPLL 5
|
||||
#define CLK_FOUT_CPLL 6
|
||||
#define CLK_FOUT_EPLL 7
|
||||
#define CLK_FOUT_VPLL 8
|
||||
|
||||
/* gate for special clocks (sclk) */
|
||||
#define CLK_SCLK_CAM_BAYER 128
|
||||
#define CLK_SCLK_CAM0 129
|
||||
#define CLK_SCLK_CAM1 130
|
||||
#define CLK_SCLK_GSCL_WA 131
|
||||
#define CLK_SCLK_GSCL_WB 132
|
||||
#define CLK_SCLK_FIMD1 133
|
||||
#define CLK_SCLK_MIPI1 134
|
||||
#define CLK_SCLK_DP 135
|
||||
#define CLK_SCLK_HDMI 136
|
||||
#define CLK_SCLK_PIXEL 137
|
||||
#define CLK_SCLK_AUDIO0 138
|
||||
#define CLK_SCLK_MMC0 139
|
||||
#define CLK_SCLK_MMC1 140
|
||||
#define CLK_SCLK_MMC2 141
|
||||
#define CLK_SCLK_MMC3 142
|
||||
#define CLK_SCLK_SATA 143
|
||||
#define CLK_SCLK_USB3 144
|
||||
#define CLK_SCLK_JPEG 145
|
||||
#define CLK_SCLK_UART0 146
|
||||
#define CLK_SCLK_UART1 147
|
||||
#define CLK_SCLK_UART2 148
|
||||
#define CLK_SCLK_UART3 149
|
||||
#define CLK_SCLK_PWM 150
|
||||
#define CLK_SCLK_AUDIO1 151
|
||||
#define CLK_SCLK_AUDIO2 152
|
||||
#define CLK_SCLK_SPDIF 153
|
||||
#define CLK_SCLK_SPI0 154
|
||||
#define CLK_SCLK_SPI1 155
|
||||
#define CLK_SCLK_SPI2 156
|
||||
#define CLK_DIV_I2S1 157
|
||||
#define CLK_DIV_I2S2 158
|
||||
#define CLK_SCLK_HDMIPHY 159
|
||||
#define CLK_DIV_PCM0 160
|
||||
|
||||
/* gate clocks */
|
||||
#define CLK_GSCL0 256
|
||||
#define CLK_GSCL1 257
|
||||
#define CLK_GSCL2 258
|
||||
#define CLK_GSCL3 259
|
||||
#define CLK_GSCL_WA 260
|
||||
#define CLK_GSCL_WB 261
|
||||
#define CLK_SMMU_GSCL0 262
|
||||
#define CLK_SMMU_GSCL1 263
|
||||
#define CLK_SMMU_GSCL2 264
|
||||
#define CLK_SMMU_GSCL3 265
|
||||
#define CLK_MFC 266
|
||||
#define CLK_SMMU_MFCL 267
|
||||
#define CLK_SMMU_MFCR 268
|
||||
#define CLK_ROTATOR 269
|
||||
#define CLK_JPEG 270
|
||||
#define CLK_MDMA1 271
|
||||
#define CLK_SMMU_ROTATOR 272
|
||||
#define CLK_SMMU_JPEG 273
|
||||
#define CLK_SMMU_MDMA1 274
|
||||
#define CLK_PDMA0 275
|
||||
#define CLK_PDMA1 276
|
||||
#define CLK_SATA 277
|
||||
#define CLK_USBOTG 278
|
||||
#define CLK_MIPI_HSI 279
|
||||
#define CLK_SDMMC0 280
|
||||
#define CLK_SDMMC1 281
|
||||
#define CLK_SDMMC2 282
|
||||
#define CLK_SDMMC3 283
|
||||
#define CLK_SROMC 284
|
||||
#define CLK_USB2 285
|
||||
#define CLK_USB3 286
|
||||
#define CLK_SATA_PHYCTRL 287
|
||||
#define CLK_SATA_PHYI2C 288
|
||||
#define CLK_UART0 289
|
||||
#define CLK_UART1 290
|
||||
#define CLK_UART2 291
|
||||
#define CLK_UART3 292
|
||||
#define CLK_UART4 293
|
||||
#define CLK_I2C0 294
|
||||
#define CLK_I2C1 295
|
||||
#define CLK_I2C2 296
|
||||
#define CLK_I2C3 297
|
||||
#define CLK_I2C4 298
|
||||
#define CLK_I2C5 299
|
||||
#define CLK_I2C6 300
|
||||
#define CLK_I2C7 301
|
||||
#define CLK_I2C_HDMI 302
|
||||
#define CLK_ADC 303
|
||||
#define CLK_SPI0 304
|
||||
#define CLK_SPI1 305
|
||||
#define CLK_SPI2 306
|
||||
#define CLK_I2S1 307
|
||||
#define CLK_I2S2 308
|
||||
#define CLK_PCM1 309
|
||||
#define CLK_PCM2 310
|
||||
#define CLK_PWM 311
|
||||
#define CLK_SPDIF 312
|
||||
#define CLK_AC97 313
|
||||
#define CLK_HSI2C0 314
|
||||
#define CLK_HSI2C1 315
|
||||
#define CLK_HSI2C2 316
|
||||
#define CLK_HSI2C3 317
|
||||
#define CLK_CHIPID 318
|
||||
#define CLK_SYSREG 319
|
||||
#define CLK_PMU 320
|
||||
#define CLK_CMU_TOP 321
|
||||
#define CLK_CMU_CORE 322
|
||||
#define CLK_CMU_MEM 323
|
||||
#define CLK_TZPC0 324
|
||||
#define CLK_TZPC1 325
|
||||
#define CLK_TZPC2 326
|
||||
#define CLK_TZPC3 327
|
||||
#define CLK_TZPC4 328
|
||||
#define CLK_TZPC5 329
|
||||
#define CLK_TZPC6 330
|
||||
#define CLK_TZPC7 331
|
||||
#define CLK_TZPC8 332
|
||||
#define CLK_TZPC9 333
|
||||
#define CLK_HDMI_CEC 334
|
||||
#define CLK_MCT 335
|
||||
#define CLK_WDT 336
|
||||
#define CLK_RTC 337
|
||||
#define CLK_TMU 338
|
||||
#define CLK_FIMD1 339
|
||||
#define CLK_MIE1 340
|
||||
#define CLK_DSIM0 341
|
||||
#define CLK_DP 342
|
||||
#define CLK_MIXER 343
|
||||
#define CLK_HDMI 344
|
||||
#define CLK_G2D 345
|
||||
#define CLK_MDMA0 346
|
||||
#define CLK_SMMU_MDMA0 347
|
||||
|
||||
/* mux clocks */
|
||||
#define CLK_MOUT_HDMI 1024
|
||||
|
||||
/* must be greater than maximal clock id */
|
||||
#define CLK_NR_CLKS 1025
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
|
||||
188
include/dt-bindings/clock/exynos5420.h
Normal file
188
include/dt-bindings/clock/exynos5420.h
Normal file
|
|
@ -0,0 +1,188 @@
|
|||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* Author: Andrzej Haja <a.hajda@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Device Tree binding constants for Exynos5420 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H
|
||||
|
||||
/* core clocks */
|
||||
#define CLK_FIN_PLL 1
|
||||
#define CLK_FOUT_APLL 2
|
||||
#define CLK_FOUT_CPLL 3
|
||||
#define CLK_FOUT_DPLL 4
|
||||
#define CLK_FOUT_EPLL 5
|
||||
#define CLK_FOUT_RPLL 6
|
||||
#define CLK_FOUT_IPLL 7
|
||||
#define CLK_FOUT_SPLL 8
|
||||
#define CLK_FOUT_VPLL 9
|
||||
#define CLK_FOUT_MPLL 10
|
||||
#define CLK_FOUT_BPLL 11
|
||||
#define CLK_FOUT_KPLL 12
|
||||
|
||||
/* gate for special clocks (sclk) */
|
||||
#define CLK_SCLK_UART0 128
|
||||
#define CLK_SCLK_UART1 129
|
||||
#define CLK_SCLK_UART2 130
|
||||
#define CLK_SCLK_UART3 131
|
||||
#define CLK_SCLK_MMC0 132
|
||||
#define CLK_SCLK_MMC1 133
|
||||
#define CLK_SCLK_MMC2 134
|
||||
#define CLK_SCLK_SPI0 135
|
||||
#define CLK_SCLK_SPI1 136
|
||||
#define CLK_SCLK_SPI2 137
|
||||
#define CLK_SCLK_I2S1 138
|
||||
#define CLK_SCLK_I2S2 139
|
||||
#define CLK_SCLK_PCM1 140
|
||||
#define CLK_SCLK_PCM2 141
|
||||
#define CLK_SCLK_SPDIF 142
|
||||
#define CLK_SCLK_HDMI 143
|
||||
#define CLK_SCLK_PIXEL 144
|
||||
#define CLK_SCLK_DP1 145
|
||||
#define CLK_SCLK_MIPI1 146
|
||||
#define CLK_SCLK_FIMD1 147
|
||||
#define CLK_SCLK_MAUDIO0 148
|
||||
#define CLK_SCLK_MAUPCM0 149
|
||||
#define CLK_SCLK_USBD300 150
|
||||
#define CLK_SCLK_USBD301 151
|
||||
#define CLK_SCLK_USBPHY300 152
|
||||
#define CLK_SCLK_USBPHY301 153
|
||||
#define CLK_SCLK_UNIPRO 154
|
||||
#define CLK_SCLK_PWM 155
|
||||
#define CLK_SCLK_GSCL_WA 156
|
||||
#define CLK_SCLK_GSCL_WB 157
|
||||
#define CLK_SCLK_HDMIPHY 158
|
||||
|
||||
/* gate clocks */
|
||||
#define CLK_ACLK66_PERIC 256
|
||||
#define CLK_UART0 257
|
||||
#define CLK_UART1 258
|
||||
#define CLK_UART2 259
|
||||
#define CLK_UART3 260
|
||||
#define CLK_I2C0 261
|
||||
#define CLK_I2C1 262
|
||||
#define CLK_I2C2 263
|
||||
#define CLK_I2C3 264
|
||||
#define CLK_I2C4 265
|
||||
#define CLK_I2C5 266
|
||||
#define CLK_I2C6 267
|
||||
#define CLK_I2C7 268
|
||||
#define CLK_I2C_HDMI 269
|
||||
#define CLK_TSADC 270
|
||||
#define CLK_SPI0 271
|
||||
#define CLK_SPI1 272
|
||||
#define CLK_SPI2 273
|
||||
#define CLK_KEYIF 274
|
||||
#define CLK_I2S1 275
|
||||
#define CLK_I2S2 276
|
||||
#define CLK_PCM1 277
|
||||
#define CLK_PCM2 278
|
||||
#define CLK_PWM 279
|
||||
#define CLK_SPDIF 280
|
||||
#define CLK_I2C8 281
|
||||
#define CLK_I2C9 282
|
||||
#define CLK_I2C10 283
|
||||
#define CLK_ACLK66_PSGEN 300
|
||||
#define CLK_CHIPID 301
|
||||
#define CLK_SYSREG 302
|
||||
#define CLK_TZPC0 303
|
||||
#define CLK_TZPC1 304
|
||||
#define CLK_TZPC2 305
|
||||
#define CLK_TZPC3 306
|
||||
#define CLK_TZPC4 307
|
||||
#define CLK_TZPC5 308
|
||||
#define CLK_TZPC6 309
|
||||
#define CLK_TZPC7 310
|
||||
#define CLK_TZPC8 311
|
||||
#define CLK_TZPC9 312
|
||||
#define CLK_HDMI_CEC 313
|
||||
#define CLK_SECKEY 314
|
||||
#define CLK_MCT 315
|
||||
#define CLK_WDT 316
|
||||
#define CLK_RTC 317
|
||||
#define CLK_TMU 318
|
||||
#define CLK_TMU_GPU 319
|
||||
#define CLK_PCLK66_GPIO 330
|
||||
#define CLK_ACLK200_FSYS2 350
|
||||
#define CLK_MMC0 351
|
||||
#define CLK_MMC1 352
|
||||
#define CLK_MMC2 353
|
||||
#define CLK_SROMC 354
|
||||
#define CLK_UFS 355
|
||||
#define CLK_ACLK200_FSYS 360
|
||||
#define CLK_TSI 361
|
||||
#define CLK_PDMA0 362
|
||||
#define CLK_PDMA1 363
|
||||
#define CLK_RTIC 364
|
||||
#define CLK_USBH20 365
|
||||
#define CLK_USBD300 366
|
||||
#define CLK_USBD301 367
|
||||
#define CLK_ACLK400_MSCL 380
|
||||
#define CLK_MSCL0 381
|
||||
#define CLK_MSCL1 382
|
||||
#define CLK_MSCL2 383
|
||||
#define CLK_SMMU_MSCL0 384
|
||||
#define CLK_SMMU_MSCL1 385
|
||||
#define CLK_SMMU_MSCL2 386
|
||||
#define CLK_ACLK333 400
|
||||
#define CLK_MFC 401
|
||||
#define CLK_SMMU_MFCL 402
|
||||
#define CLK_SMMU_MFCR 403
|
||||
#define CLK_ACLK200_DISP1 410
|
||||
#define CLK_DSIM1 411
|
||||
#define CLK_DP1 412
|
||||
#define CLK_HDMI 413
|
||||
#define CLK_ACLK300_DISP1 420
|
||||
#define CLK_FIMD1 421
|
||||
#define CLK_SMMU_FIMD1 422
|
||||
#define CLK_ACLK166 430
|
||||
#define CLK_MIXER 431
|
||||
#define CLK_ACLK266 440
|
||||
#define CLK_ROTATOR 441
|
||||
#define CLK_MDMA1 442
|
||||
#define CLK_SMMU_ROTATOR 443
|
||||
#define CLK_SMMU_MDMA1 444
|
||||
#define CLK_ACLK300_JPEG 450
|
||||
#define CLK_JPEG 451
|
||||
#define CLK_JPEG2 452
|
||||
#define CLK_SMMU_JPEG 453
|
||||
#define CLK_ACLK300_GSCL 460
|
||||
#define CLK_SMMU_GSCL0 461
|
||||
#define CLK_SMMU_GSCL1 462
|
||||
#define CLK_GSCL_WA 463
|
||||
#define CLK_GSCL_WB 464
|
||||
#define CLK_GSCL0 465
|
||||
#define CLK_GSCL1 466
|
||||
#define CLK_CLK_3AA 467
|
||||
#define CLK_ACLK266_G2D 470
|
||||
#define CLK_SSS 471
|
||||
#define CLK_SLIM_SSS 472
|
||||
#define CLK_MDMA0 473
|
||||
#define CLK_ACLK333_G2D 480
|
||||
#define CLK_G2D 481
|
||||
#define CLK_ACLK333_432_GSCL 490
|
||||
#define CLK_SMMU_3AA 491
|
||||
#define CLK_SMMU_FIMCL0 492
|
||||
#define CLK_SMMU_FIMCL1 493
|
||||
#define CLK_SMMU_FIMCL3 494
|
||||
#define CLK_FIMC_LITE3 495
|
||||
#define CLK_ACLK_G3D 500
|
||||
#define CLK_G3D 501
|
||||
#define CLK_SMMU_MIXER 502
|
||||
|
||||
/* mux clocks */
|
||||
#define CLK_MOUT_HDMI 640
|
||||
|
||||
/* divider clocks */
|
||||
#define CLK_DOUT_PIXEL 768
|
||||
|
||||
/* must be greater than maximal clock id */
|
||||
#define CLK_NR_CLKS 769
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
|
||||
42
include/dt-bindings/clock/exynos5440.h
Normal file
42
include/dt-bindings/clock/exynos5440.h
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* Author: Andrzej Haja <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Device Tree binding constants for Exynos5440 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5440_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS_5440_H
|
||||
|
||||
#define CLK_XTAL 1
|
||||
#define CLK_ARM_CLK 2
|
||||
#define CLK_SPI_BAUD 16
|
||||
#define CLK_PB0_250 17
|
||||
#define CLK_PR0_250 18
|
||||
#define CLK_PR1_250 19
|
||||
#define CLK_B_250 20
|
||||
#define CLK_B_125 21
|
||||
#define CLK_B_200 22
|
||||
#define CLK_SATA 23
|
||||
#define CLK_USB 24
|
||||
#define CLK_GMAC0 25
|
||||
#define CLK_CS250 26
|
||||
#define CLK_PB0_250_O 27
|
||||
#define CLK_PR0_250_O 28
|
||||
#define CLK_PR1_250_O 29
|
||||
#define CLK_B_250_O 30
|
||||
#define CLK_B_125_O 31
|
||||
#define CLK_B_200_O 32
|
||||
#define CLK_SATA_O 33
|
||||
#define CLK_USB_O 34
|
||||
#define CLK_GMAC0_O 35
|
||||
#define CLK_CS250_O 36
|
||||
|
||||
/* must be greater than maximal clock id */
|
||||
#define CLK_NR_CLKS 37
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5440_H */
|
||||
Loading…
Reference in a new issue