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arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal 

This reset signal controls the Marvell 1512 1G PHY.

Note that current implementation queries the PHY over the MDIO bus
(get_phy_device() call from of_mdiobus_register_phy()) before reset
signal deassert. If the PHY reset signal is asserted at boot time, PHY
registration fails. So current code relies on the bootloader to deassert
the reset signal.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
hifive-unleashed-5.1
Baruch Siach 2018-10-16 13:50:53 +03:00 committed by Gregory CLEMENT
parent b597a6f542
commit babc5544c2
1 changed files with 4 additions and 0 deletions
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4
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
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@ -333,6 +333,10 @@
*/
marvell,reg-init = <3 16 0 0x1017>;
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&cp0_copper_eth_phy_reset>;
reset-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
};
switch0: switch0@4 {