Merge branch 'remotes/lorenzo/pci/rcar'
- Use BIT() when appropriate in rcar (Marek Vasut) - Use u32 to match rcar hardware register widths (Marek Vasut) - Use BITS_PER_BYTE when appropriate in rcar (Marek Vasut) - Remove unnecessary casts in rcar (Marek Vasut) - Fix 64-bit MSI target addresses in rcar (Marek Vasut) - Check for __get_free_pages() failure in rcar (Kangjie Lu) - Fix shadowed rcar "irq" variable (Wolfram Sang) * remotes/lorenzo/pci/rcar: PCI: rcar: Do not shadow the 'irq' variable PCI: rcar: Fix a potential NULL pointer dereference PCI: rcar: Fix 64bit MSI message address handling PCI: rcar: Clean up debug messages PCI: rcar: Replace (8 * n) with (BITS_PER_BYTE * n) PCI: rcar: Replace various variable types with unsigned ones for register values PCI: rcar: Replace unsigned long with u32/unsigned int in register accessors PCI: rcar: Clean up remaining macros defining bits # Conflicts: # drivers/pci/controller/pcie-rcar.chifive-unleashed-5.2
Bjorn Helgaas
commit
bac9789e53
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@ -47,14 +47,14 @@
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/* Transfer control */
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#define PCIETCTLR 0x02000
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#define DL_DOWN BIT(3)
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#define CFINIT 1
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#define CFINIT BIT(0)
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#define PCIETSTR 0x02004
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#define DATA_LINK_ACTIVE 1
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#define DATA_LINK_ACTIVE BIT(0)
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#define PCIEERRFR 0x02020
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#define UNSUPPORTED_REQUEST BIT(4)
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#define PCIEMSIFR 0x02044
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#define PCIEMSIALR 0x02048
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#define MSIFE 1
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#define MSIFE BIT(0)
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#define PCIEMSIAUR 0x0204c
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#define PCIEMSIIER 0x02050
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@ -154,14 +154,13 @@ struct rcar_pcie {
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struct rcar_msi msi;
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};
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static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
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unsigned long reg)
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static void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val,
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unsigned int reg)
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{
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writel(val, pcie->base + reg);
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}
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static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
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unsigned long reg)
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static u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg)
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{
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return readl(pcie->base + reg);
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}
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@ -173,7 +172,7 @@ enum {
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static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
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{
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int shift = 8 * (where & 3);
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unsigned int shift = BITS_PER_BYTE * (where & 3);
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u32 val = rcar_pci_read_reg(pcie, where & ~3);
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val &= ~(mask << shift);
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@ -183,7 +182,7 @@ static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
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static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
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{
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int shift = 8 * (where & 3);
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unsigned int shift = BITS_PER_BYTE * (where & 3);
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u32 val = rcar_pci_read_reg(pcie, where & ~3);
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return val >> shift;
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@ -194,7 +193,7 @@ static int rcar_pcie_config_access(struct rcar_pcie *pcie,
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unsigned char access_type, struct pci_bus *bus,
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unsigned int devfn, int where, u32 *data)
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{
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int dev, func, reg, index;
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unsigned int dev, func, reg, index;
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dev = PCI_SLOT(devfn);
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func = PCI_FUNC(devfn);
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@ -283,12 +282,12 @@ static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
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}
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if (size == 1)
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*val = (*val >> (8 * (where & 3))) & 0xff;
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*val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff;
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else if (size == 2)
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*val = (*val >> (8 * (where & 2))) & 0xffff;
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*val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff;
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dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
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bus->number, devfn, where, size, (unsigned long)*val);
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dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
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bus->number, devfn, where, size, *val);
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return ret;
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}
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@ -298,23 +297,24 @@ static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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struct rcar_pcie *pcie = bus->sysdata;
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int shift, ret;
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unsigned int shift;
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u32 data;
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int ret;
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ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
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bus, devfn, where, &data);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
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bus->number, devfn, where, size, (unsigned long)val);
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dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
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bus->number, devfn, where, size, val);
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if (size == 1) {
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shift = 8 * (where & 3);
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shift = BITS_PER_BYTE * (where & 3);
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data &= ~(0xff << shift);
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data |= ((val & 0xff) << shift);
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} else if (size == 2) {
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shift = 8 * (where & 2);
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shift = BITS_PER_BYTE * (where & 2);
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data &= ~(0xffff << shift);
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data |= ((val & 0xffff) << shift);
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} else
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@ -509,10 +509,10 @@ static int phy_wait_for_ack(struct rcar_pcie *pcie)
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}
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static void phy_write_reg(struct rcar_pcie *pcie,
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unsigned int rate, unsigned int addr,
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unsigned int lane, unsigned int data)
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unsigned int rate, u32 addr,
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unsigned int lane, u32 data)
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{
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unsigned long phyaddr;
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u32 phyaddr;
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phyaddr = WRITE_CMD |
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((rate & 1) << RATE_POS) |
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@ -740,15 +740,15 @@ static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
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while (reg) {
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unsigned int index = find_first_bit(®, 32);
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unsigned int irq;
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unsigned int msi_irq;
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/* clear the interrupt */
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rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
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irq = irq_find_mapping(msi->domain, index);
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if (irq) {
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msi_irq = irq_find_mapping(msi->domain, index);
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if (msi_irq) {
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if (test_bit(index, msi->used))
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generic_handle_irq(irq);
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generic_handle_irq(msi_irq);
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else
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dev_info(dev, "unhandled MSI\n");
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} else {
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@ -892,7 +892,7 @@ static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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struct rcar_msi *msi = &pcie->msi;
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unsigned long base;
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phys_addr_t base;
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int err, i;
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mutex_init(&msi->lock);
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@ -931,10 +931,14 @@ static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
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/* setup MSI data target */
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msi->pages = __get_free_pages(GFP_KERNEL, 0);
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if (!msi->pages) {
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err = -ENOMEM;
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goto err;
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}
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base = virt_to_phys((void *)msi->pages);
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rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
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rcar_pci_write_reg(pcie, 0, PCIEMSIAUR);
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rcar_pci_write_reg(pcie, lower_32_bits(base) | MSIFE, PCIEMSIALR);
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rcar_pci_write_reg(pcie, upper_32_bits(base), PCIEMSIAUR);
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/* enable all MSI interrupts */
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rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
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@ -1120,7 +1124,7 @@ static int rcar_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rcar_pcie *pcie;
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unsigned int data;
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u32 data;
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int err;
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int (*phy_init_fn)(struct rcar_pcie *);
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struct pci_host_bridge *bridge;
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