drm/i915: Track full cdclk state for the logical and actual cdclk frequencies
The current dev_cdclk vs. cdclk vs. atomic_cdclk_freq is quite a mess. So here I'm introducing the "actual" and "logical" naming for our cdclk state. "actual" is what we'll bash into the hardware and "logical" is what everyone should use for state computaion/checking and whatnot. We'll track both using the intel_cdclk_state as both will need other differing parameters than just the actual cdclk frequency. While doing that we can at the same time unify the appearance of the .modeset_calc_cdclk() implementations a little bit. v2: Commit dev_priv->cdclk.actual since that already has the new state by the time .modeset_commit_cdclk() is called. v3: s/locical/logical/ and improve the docs a bit Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170120182205.8141-9-ville.syrjala@linux.intel.com
This commit is contained in:
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@ -2172,18 +2172,26 @@ struct drm_i915_private {
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unsigned int skl_preferred_vco_freq;
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unsigned int max_cdclk_freq;
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/*
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* For reading holding any crtc lock is sufficient,
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* for writing must hold all of them.
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*/
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unsigned int atomic_cdclk_freq;
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unsigned int max_dotclk_freq;
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unsigned int rawclk_freq;
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unsigned int hpll_freq;
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unsigned int czclk_freq;
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struct {
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/*
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* The current logical cdclk state.
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* See intel_atomic_state.cdclk.logical
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*
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* For reading holding any crtc lock is sufficient,
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* for writing must hold all of them.
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*/
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struct intel_cdclk_state logical;
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/*
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* The current actual cdclk state.
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* See intel_atomic_state.cdclk.actual
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*/
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struct intel_cdclk_state actual;
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/* The current hardware cdclk state */
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struct intel_cdclk_state hw;
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} cdclk;
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@ -1460,12 +1460,26 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
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int max_pixclk = intel_max_pixel_rate(state);
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struct intel_atomic_state *intel_state =
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to_intel_atomic_state(state);
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int cdclk;
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intel_state->cdclk = intel_state->dev_cdclk =
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vlv_calc_cdclk(dev_priv, max_pixclk);
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cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
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if (!intel_state->active_crtcs)
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intel_state->dev_cdclk = vlv_calc_cdclk(dev_priv, 0);
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if (cdclk > dev_priv->max_cdclk_freq) {
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DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
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cdclk, dev_priv->max_cdclk_freq);
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return -EINVAL;
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}
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intel_state->cdclk.logical.cdclk = cdclk;
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if (!intel_state->active_crtcs) {
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cdclk = vlv_calc_cdclk(dev_priv, 0);
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intel_state->cdclk.actual.cdclk = cdclk;
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} else {
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intel_state->cdclk.actual =
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intel_state->cdclk.logical;
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}
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return 0;
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}
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@ -1474,9 +1488,7 @@ static void vlv_modeset_commit_cdclk(struct drm_atomic_state *old_state)
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{
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struct drm_device *dev = old_state->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_atomic_state *old_intel_state =
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to_intel_atomic_state(old_state);
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unsigned int req_cdclk = old_intel_state->dev_cdclk;
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unsigned int req_cdclk = dev_priv->cdclk.actual.cdclk;
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/*
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* FIXME: We can end up here with all power domains off, yet
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@ -1518,9 +1530,16 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
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return -EINVAL;
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}
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intel_state->cdclk = intel_state->dev_cdclk = cdclk;
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if (!intel_state->active_crtcs)
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intel_state->dev_cdclk = bdw_calc_cdclk(0);
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intel_state->cdclk.logical.cdclk = cdclk;
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if (!intel_state->active_crtcs) {
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cdclk = bdw_calc_cdclk(0);
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intel_state->cdclk.actual.cdclk = cdclk;
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} else {
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intel_state->cdclk.actual =
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intel_state->cdclk.logical;
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}
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return 0;
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}
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@ -1528,9 +1547,7 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
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static void bdw_modeset_commit_cdclk(struct drm_atomic_state *old_state)
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{
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struct drm_device *dev = old_state->dev;
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struct intel_atomic_state *old_intel_state =
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to_intel_atomic_state(old_state);
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unsigned int req_cdclk = old_intel_state->dev_cdclk;
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unsigned int req_cdclk = to_i915(dev)->cdclk.actual.cdclk;
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bdw_set_cdclk(dev, req_cdclk);
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}
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@ -1540,8 +1557,11 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
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struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
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struct drm_i915_private *dev_priv = to_i915(state->dev);
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const int max_pixclk = intel_max_pixel_rate(state);
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int vco = intel_state->cdclk_pll_vco;
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int cdclk;
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int cdclk, vco;
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vco = intel_state->cdclk.logical.vco;
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if (!vco)
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vco = dev_priv->skl_preferred_vco_freq;
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/*
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* FIXME should also account for plane ratio
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@ -1549,19 +1569,24 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
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*/
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cdclk = skl_calc_cdclk(max_pixclk, vco);
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/*
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* FIXME move the cdclk caclulation to
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* compute_config() so we can fail gracegully.
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*/
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if (cdclk > dev_priv->max_cdclk_freq) {
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DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
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cdclk, dev_priv->max_cdclk_freq);
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cdclk = dev_priv->max_cdclk_freq;
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DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
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cdclk, dev_priv->max_cdclk_freq);
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return -EINVAL;
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}
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intel_state->cdclk = intel_state->dev_cdclk = cdclk;
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if (!intel_state->active_crtcs)
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intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
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intel_state->cdclk.logical.vco = vco;
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intel_state->cdclk.logical.cdclk = cdclk;
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if (!intel_state->active_crtcs) {
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cdclk = skl_calc_cdclk(0, vco);
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intel_state->cdclk.actual.vco = vco;
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intel_state->cdclk.actual.cdclk = cdclk;
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} else {
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intel_state->cdclk.actual =
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intel_state->cdclk.logical;
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}
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return 0;
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}
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@ -1569,10 +1594,8 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
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static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
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{
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struct drm_i915_private *dev_priv = to_i915(old_state->dev);
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struct intel_atomic_state *intel_state =
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to_intel_atomic_state(old_state);
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unsigned int req_cdclk = intel_state->dev_cdclk;
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unsigned int req_vco = intel_state->cdclk_pll_vco;
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unsigned int req_cdclk = dev_priv->cdclk.actual.cdclk;
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unsigned int req_vco = dev_priv->cdclk.actual.vco;
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skl_set_cdclk(dev_priv, req_cdclk, req_vco);
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}
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@ -1583,22 +1606,39 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
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int max_pixclk = intel_max_pixel_rate(state);
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struct intel_atomic_state *intel_state =
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to_intel_atomic_state(state);
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int cdclk;
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int cdclk, vco;
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if (IS_GEMINILAKE(dev_priv))
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if (IS_GEMINILAKE(dev_priv)) {
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cdclk = glk_calc_cdclk(max_pixclk);
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else
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vco = glk_de_pll_vco(dev_priv, cdclk);
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} else {
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cdclk = bxt_calc_cdclk(max_pixclk);
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vco = bxt_de_pll_vco(dev_priv, cdclk);
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}
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intel_state->cdclk = intel_state->dev_cdclk = cdclk;
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if (cdclk > dev_priv->max_cdclk_freq) {
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DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
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cdclk, dev_priv->max_cdclk_freq);
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return -EINVAL;
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}
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intel_state->cdclk.logical.vco = vco;
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intel_state->cdclk.logical.cdclk = cdclk;
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if (!intel_state->active_crtcs) {
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if (IS_GEMINILAKE(dev_priv))
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if (IS_GEMINILAKE(dev_priv)) {
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cdclk = glk_calc_cdclk(0);
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else
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vco = glk_de_pll_vco(dev_priv, cdclk);
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} else {
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cdclk = bxt_calc_cdclk(0);
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vco = bxt_de_pll_vco(dev_priv, cdclk);
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}
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intel_state->dev_cdclk = cdclk;
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intel_state->cdclk.actual.vco = vco;
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intel_state->cdclk.actual.cdclk = cdclk;
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} else {
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intel_state->cdclk.actual =
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intel_state->cdclk.logical;
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}
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return 0;
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@ -1607,15 +1647,8 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
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static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
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{
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struct drm_i915_private *dev_priv = to_i915(old_state->dev);
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struct intel_atomic_state *old_intel_state =
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to_intel_atomic_state(old_state);
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unsigned int req_cdclk = old_intel_state->dev_cdclk;
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unsigned int req_vco;
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if (IS_GEMINILAKE(dev_priv))
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req_vco = glk_de_pll_vco(dev_priv, req_cdclk);
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else
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req_vco = bxt_de_pll_vco(dev_priv, req_cdclk);
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unsigned int req_cdclk = dev_priv->cdclk.actual.cdclk;
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unsigned int req_vco = dev_priv->cdclk.actual.vco;
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bxt_set_cdclk(dev_priv, req_cdclk, req_vco);
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}
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@ -12393,6 +12393,8 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
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intel_state->modeset = true;
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intel_state->active_crtcs = dev_priv->active_crtcs;
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intel_state->cdclk.logical = dev_priv->cdclk.logical;
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intel_state->cdclk.actual = dev_priv->cdclk.actual;
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for_each_crtc_in_state(state, crtc, crtc_state, i) {
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if (crtc_state->active)
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@ -12412,38 +12414,35 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
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* adjusted_mode bits in the crtc directly.
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*/
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if (dev_priv->display.modeset_calc_cdclk) {
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if (!intel_state->cdclk_pll_vco)
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intel_state->cdclk_pll_vco = dev_priv->cdclk.hw.vco;
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if (!intel_state->cdclk_pll_vco)
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intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
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ret = dev_priv->display.modeset_calc_cdclk(state);
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if (ret < 0)
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return ret;
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/*
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* Writes to dev_priv->atomic_cdclk_freq must protected by
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* Writes to dev_priv->cdclk.logical must protected by
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* holding all the crtc locks, even if we don't end up
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* touching the hardware
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*/
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if (intel_state->cdclk != dev_priv->atomic_cdclk_freq) {
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if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
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&intel_state->cdclk.logical)) {
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ret = intel_lock_all_pipes(state);
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if (ret < 0)
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return ret;
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}
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/* All pipes must be switched off while we change the cdclk. */
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if (intel_state->dev_cdclk != dev_priv->cdclk.hw.cdclk ||
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intel_state->cdclk_pll_vco != dev_priv->cdclk.hw.vco) {
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if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
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&intel_state->cdclk.actual)) {
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ret = intel_modeset_all_pipes(state);
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if (ret < 0)
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return ret;
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}
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DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
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intel_state->cdclk, intel_state->dev_cdclk);
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DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
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intel_state->cdclk.logical.cdclk,
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intel_state->cdclk.actual.cdclk);
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} else {
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to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
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to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
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}
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intel_modeset_clear_plls(state);
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@ -12546,7 +12545,7 @@ static int intel_atomic_check(struct drm_device *dev,
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if (ret)
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return ret;
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} else {
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intel_state->cdclk = dev_priv->atomic_cdclk_freq;
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intel_state->cdclk.logical = dev_priv->cdclk.logical;
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}
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ret = drm_atomic_helper_check_planes(dev, state);
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@ -12869,8 +12868,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
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drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
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if (dev_priv->display.modeset_commit_cdclk &&
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(intel_state->dev_cdclk != dev_priv->cdclk.hw.cdclk ||
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intel_state->cdclk_pll_vco != dev_priv->cdclk.hw.vco))
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!intel_cdclk_state_compare(&dev_priv->cdclk.hw,
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&dev_priv->cdclk.actual))
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dev_priv->display.modeset_commit_cdclk(state);
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/*
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@ -13059,7 +13058,8 @@ static int intel_atomic_commit(struct drm_device *dev,
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memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
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sizeof(intel_state->min_pixclk));
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dev_priv->active_crtcs = intel_state->active_crtcs;
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dev_priv->atomic_cdclk_freq = intel_state->cdclk;
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dev_priv->cdclk.logical = intel_state->cdclk.logical;
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dev_priv->cdclk.actual = intel_state->cdclk.actual;
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}
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drm_atomic_state_get(state);
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@ -13297,7 +13297,7 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
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return DRM_PLANE_HELPER_NO_SCALING;
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crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
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cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
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cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
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if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
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return DRM_PLANE_HELPER_NO_SCALING;
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@ -14854,8 +14854,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
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struct drm_i915_private *dev_priv = to_i915(dev);
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intel_update_cdclk(dev_priv);
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dev_priv->atomic_cdclk_freq = dev_priv->cdclk.hw.cdclk;
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dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
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intel_init_clock_gating(dev_priv);
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}
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@ -15031,7 +15030,7 @@ int intel_modeset_init(struct drm_device *dev)
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intel_update_czclk(dev_priv);
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intel_update_cdclk(dev_priv);
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dev_priv->atomic_cdclk_freq = dev_priv->cdclk.hw.cdclk;
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dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
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intel_shared_dpll_init(dev);
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@ -1785,7 +1785,7 @@ found:
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break;
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}
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to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
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to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
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}
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if (!HAS_DDI(dev_priv))
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@ -333,13 +333,20 @@ struct dpll {
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struct intel_atomic_state {
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struct drm_atomic_state base;
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unsigned int cdclk;
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struct {
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/*
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* Logical state of cdclk (used for all scaling, watermark,
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* etc. calculations and checks). This is computed as if all
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* enabled crtcs were active.
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*/
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struct intel_cdclk_state logical;
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/*
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* Calculated device cdclk, can be different from cdclk
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* only when all crtc's are DPMS off.
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*/
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unsigned int dev_cdclk;
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/*
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* Actual state of cdclk, can be different from the logical
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* state only when all crtc's are DPMS off.
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*/
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struct intel_cdclk_state actual;
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} cdclk;
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bool dpll_set, modeset;
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@ -356,9 +363,6 @@ struct intel_atomic_state {
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unsigned int active_crtcs;
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unsigned int min_pixclk[I915_MAX_PIPES];
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/* SKL/KBL Only */
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unsigned int cdclk_pll_vco;
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struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
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/*
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@ -2108,7 +2108,7 @@ hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
|
|||
return 0;
|
||||
if (WARN_ON(adjusted_mode->crtc_clock == 0))
|
||||
return 0;
|
||||
if (WARN_ON(intel_state->cdclk == 0))
|
||||
if (WARN_ON(intel_state->cdclk.logical.cdclk == 0))
|
||||
return 0;
|
||||
|
||||
/* The WM are computed with base on how long it takes to fill a single
|
||||
|
@ -2117,7 +2117,7 @@ hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
|
|||
linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
|
||||
adjusted_mode->crtc_clock);
|
||||
ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
|
||||
intel_state->cdclk);
|
||||
intel_state->cdclk.logical.cdclk);
|
||||
|
||||
return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
|
||||
PIPE_WM_LINETIME_TIME(linetime);
|
||||
|
|
Loading…
Reference in a new issue