drm/amdgpu: Set FreeSync state using drm VRR properties
Support for AMDGPU specific FreeSync properties and ioctls are dropped
from amdgpu_dm in favor of supporting drm variable refresh rate
properties.
The notify_freesync and set_freesync_property functions are dropped
from amdgpu_display_funcs.
The drm vrr_capable property is now attached to any DP/HDMI connector.
Its value is updated accordingly to the connector's FreeSync capabiltiy.
The freesync_enable logic and ioctl control has has been dropped in
favor of utilizing the vrr_enabled on the drm CRTC. This allows for more
fine grained atomic control over which CRTCs should support variable
refresh rate.
To handle state changes for vrr_enabled it was easiest to drop the
forced modeset on freesync_enabled change. This patch now performs the
required stream updates when planes are flipped.
This is done for a few reasons:
(1) VRR stream updates can be done in the fast update path
(2) amdgpu_dm_atomic_check would need to be hacked apart to check
desired variable refresh state and capability before the CRTC
disable pass.
(3) Performing VRR stream updates on-flip is needed for enabling BTR
support.
VRR packets and timing adjustments are now tracked and compared to
previous values sent to the hardware.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hifive-unleashed-5.1
Nicholas Kazlauskas
Alex Deucher
parent
520f08df45
commit
bb47de7366
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@ -293,13 +293,6 @@ struct amdgpu_display_funcs {
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uint16_t connector_object_id,
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struct amdgpu_hpd *hpd,
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struct amdgpu_router *router);
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/* it is used to enter or exit into free sync mode */
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int (*notify_freesync)(struct drm_device *dev, void *data,
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struct drm_file *filp);
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/* it is used to allow enablement of freesync mode */
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int (*set_freesync_property)(struct drm_connector *connector,
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struct drm_property *property,
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uint64_t val);
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};
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@ -2010,73 +2010,6 @@ static void dm_bandwidth_update(struct amdgpu_device *adev)
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/* TODO: implement later */
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}
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static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
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struct drm_file *filp)
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{
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struct drm_atomic_state *state;
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struct drm_modeset_acquire_ctx ctx;
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struct drm_crtc *crtc;
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struct drm_connector *connector;
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struct drm_connector_state *old_con_state, *new_con_state;
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int ret = 0;
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uint8_t i;
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bool enable = false;
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drm_modeset_acquire_init(&ctx, 0);
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state = drm_atomic_state_alloc(dev);
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if (!state) {
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ret = -ENOMEM;
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goto out;
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}
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state->acquire_ctx = &ctx;
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retry:
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drm_for_each_crtc(crtc, dev) {
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ret = drm_atomic_add_affected_connectors(state, crtc);
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if (ret)
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goto fail;
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/* TODO rework amdgpu_dm_commit_planes so we don't need this */
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ret = drm_atomic_add_affected_planes(state, crtc);
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if (ret)
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goto fail;
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}
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for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
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struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
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struct drm_crtc_state *new_crtc_state;
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
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struct dm_crtc_state *dm_new_crtc_state;
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if (!acrtc) {
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ASSERT(0);
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continue;
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}
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new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
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dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
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dm_new_crtc_state->freesync_enabled = enable;
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}
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ret = drm_atomic_commit(state);
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fail:
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if (ret == -EDEADLK) {
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drm_atomic_state_clear(state);
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drm_modeset_backoff(&ctx);
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goto retry;
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}
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drm_atomic_state_put(state);
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out:
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drm_modeset_drop_locks(&ctx);
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drm_modeset_acquire_fini(&ctx);
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return ret;
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}
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static const struct amdgpu_display_funcs dm_display_funcs = {
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.bandwidth_update = dm_bandwidth_update, /* called unconditionally */
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.vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
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@ -2089,8 +2022,6 @@ static const struct amdgpu_display_funcs dm_display_funcs = {
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dm_crtc_get_scanoutpos,/* called unconditionally */
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.add_encoder = NULL, /* VBIOS parsing. DAL does it. */
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.add_connector = NULL, /* VBIOS parsing. DAL does it. */
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.notify_freesync = amdgpu_notify_freesync,
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};
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#if defined(CONFIG_DEBUG_KERNEL_DC)
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@ -3068,8 +2999,9 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
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state->adjust = cur->adjust;
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state->vrr_infopacket = cur->vrr_infopacket;
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state->freesync_enabled = cur->freesync_enabled;
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state->abm_level = cur->abm_level;
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state->vrr_supported = cur->vrr_supported;
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state->freesync_config = cur->freesync_config;
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/* TODO Duplicate dc_stream after objects are stream object is flattened */
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@ -3303,7 +3235,6 @@ amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
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__drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
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new_state->freesync_capable = state->freesync_capable;
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new_state->freesync_enable = state->freesync_enable;
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new_state->abm_level = state->abm_level;
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return &new_state->base;
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@ -4059,6 +3990,12 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
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drm_object_attach_property(&aconnector->base.base,
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adev->mode_info.abm_level_property, 0);
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}
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if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
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connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
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drm_connector_attach_vrr_capable_property(
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&aconnector->base);
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}
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}
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static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
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@ -4449,6 +4386,77 @@ struct dc_stream_status *dc_state_get_stream_status(
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return NULL;
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}
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static void update_freesync_state_on_stream(
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struct amdgpu_display_manager *dm,
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struct dm_crtc_state *new_crtc_state,
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struct dc_stream_state *new_stream)
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{
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struct mod_vrr_params vrr = {0};
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struct dc_info_packet vrr_infopacket = {0};
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struct mod_freesync_config config = new_crtc_state->freesync_config;
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if (!new_stream)
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return;
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/*
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* TODO: Determine why min/max totals and vrefresh can be 0 here.
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* For now it's sufficient to just guard against these conditions.
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*/
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if (!new_stream->timing.h_total || !new_stream->timing.v_total)
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return;
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if (new_crtc_state->vrr_supported &&
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config.min_refresh_in_uhz &&
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config.max_refresh_in_uhz) {
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config.state = new_crtc_state->base.vrr_enabled ?
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VRR_STATE_ACTIVE_VARIABLE :
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VRR_STATE_INACTIVE;
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} else {
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config.state = VRR_STATE_UNSUPPORTED;
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}
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mod_freesync_build_vrr_params(dm->freesync_module,
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new_stream,
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&config, &vrr);
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mod_freesync_build_vrr_infopacket(
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dm->freesync_module,
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new_stream,
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&vrr,
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packet_type_vrr,
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transfer_func_unknown,
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&vrr_infopacket);
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new_crtc_state->freesync_timing_changed =
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(memcmp(&new_crtc_state->adjust,
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&vrr.adjust,
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sizeof(vrr.adjust)) != 0);
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new_crtc_state->freesync_vrr_info_changed =
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(memcmp(&new_crtc_state->vrr_infopacket,
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&vrr_infopacket,
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sizeof(vrr_infopacket)) != 0);
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new_crtc_state->adjust = vrr.adjust;
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new_crtc_state->vrr_infopacket = vrr_infopacket;
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new_stream->adjust = new_crtc_state->adjust;
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new_stream->vrr_infopacket = vrr_infopacket;
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if (new_crtc_state->freesync_vrr_info_changed)
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DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
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new_crtc_state->base.crtc->base.id,
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(int)new_crtc_state->base.vrr_enabled,
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(int)vrr.state);
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if (new_crtc_state->freesync_timing_changed)
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DRM_DEBUG_KMS("VRR timing update: crtc=%u min=%u max=%u\n",
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new_crtc_state->base.crtc->base.id,
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vrr.adjust.v_total_min,
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vrr.adjust.v_total_max);
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}
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/*
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* Executes flip
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*
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@ -4470,6 +4478,7 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
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struct dc_flip_addrs addr = { {0} };
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/* TODO eliminate or rename surface_update */
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struct dc_surface_update surface_updates[1] = { {0} };
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struct dc_stream_update stream_update = {0};
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struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
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struct dc_stream_status *stream_status;
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@ -4542,11 +4551,26 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
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}
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surface_updates->flip_addr = &addr;
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if (acrtc_state->stream) {
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update_freesync_state_on_stream(
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&adev->dm,
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acrtc_state,
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acrtc_state->stream);
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if (acrtc_state->freesync_timing_changed)
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stream_update.adjust =
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&acrtc_state->stream->adjust;
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if (acrtc_state->freesync_vrr_info_changed)
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stream_update.vrr_infopacket =
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&acrtc_state->stream->vrr_infopacket;
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}
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dc_commit_updates_for_stream(adev->dm.dc,
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surface_updates,
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1,
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acrtc_state->stream,
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NULL,
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&stream_update,
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&surface_updates->surface,
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state);
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@ -4607,11 +4631,6 @@ static bool commit_planes_to_stream(
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stream_update->dst = dc_stream->dst;
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stream_update->out_transfer_func = dc_stream->out_transfer_func;
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if (dm_new_crtc_state->freesync_enabled != dm_old_crtc_state->freesync_enabled) {
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stream_update->vrr_infopacket = &dc_stream->vrr_infopacket;
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stream_update->adjust = &dc_stream->adjust;
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}
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if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) {
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abm_level = dm_new_crtc_state->abm_level;
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stream_update->abm_level = &abm_level;
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@ -4752,8 +4771,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
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}
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dc_stream_attach->adjust = acrtc_state->adjust;
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dc_stream_attach->vrr_infopacket = acrtc_state->vrr_infopacket;
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dc_stream_attach->abm_level = acrtc_state->abm_level;
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if (false == commit_planes_to_stream(dm->dc,
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@ -4984,8 +5001,6 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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WARN_ON(!status);
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WARN_ON(!status->plane_count);
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dm_new_crtc_state->stream->adjust = dm_new_crtc_state->adjust;
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dm_new_crtc_state->stream->vrr_infopacket = dm_new_crtc_state->vrr_infopacket;
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dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
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/*TODO How it works with MPO ?*/
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@ -5215,20 +5230,18 @@ static int do_aquire_global_lock(struct drm_device *dev,
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return ret < 0 ? ret : 0;
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}
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void set_freesync_on_stream(struct amdgpu_display_manager *dm,
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struct dm_crtc_state *new_crtc_state,
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struct dm_connector_state *new_con_state,
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struct dc_stream_state *new_stream)
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static void get_freesync_config_for_crtc(
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struct dm_crtc_state *new_crtc_state,
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struct dm_connector_state *new_con_state)
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{
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struct mod_freesync_config config = {0};
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struct mod_vrr_params vrr = {0};
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struct dc_info_packet vrr_infopacket = {0};
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struct amdgpu_dm_connector *aconnector =
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to_amdgpu_dm_connector(new_con_state->base.connector);
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if (new_con_state->freesync_capable &&
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new_con_state->freesync_enable) {
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config.state = new_crtc_state->freesync_enabled ?
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new_crtc_state->vrr_supported = new_con_state->freesync_capable;
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if (new_con_state->freesync_capable) {
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config.state = new_crtc_state->base.vrr_enabled ?
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VRR_STATE_ACTIVE_VARIABLE :
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VRR_STATE_INACTIVE;
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config.min_refresh_in_uhz =
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@ -5238,19 +5251,18 @@ void set_freesync_on_stream(struct amdgpu_display_manager *dm,
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config.vsif_supported = true;
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}
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mod_freesync_build_vrr_params(dm->freesync_module,
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new_stream,
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&config, &vrr);
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new_crtc_state->freesync_config = config;
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}
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mod_freesync_build_vrr_infopacket(dm->freesync_module,
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new_stream,
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&vrr,
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packet_type_fs1,
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NULL,
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&vrr_infopacket);
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static void reset_freesync_config_for_crtc(
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struct dm_crtc_state *new_crtc_state)
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{
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new_crtc_state->vrr_supported = false;
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new_crtc_state->adjust = vrr.adjust;
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new_crtc_state->vrr_infopacket = vrr_infopacket;
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memset(&new_crtc_state->adjust, 0,
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sizeof(new_crtc_state->adjust));
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memset(&new_crtc_state->vrr_infopacket, 0,
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sizeof(new_crtc_state->vrr_infopacket));
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}
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static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
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@ -5326,9 +5338,6 @@ static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
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break;
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}
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set_freesync_on_stream(dm, dm_new_crtc_state,
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dm_new_conn_state, new_stream);
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dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
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if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
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@ -5339,9 +5348,6 @@ static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
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}
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}
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if (dm_old_crtc_state->freesync_enabled != dm_new_crtc_state->freesync_enabled)
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new_crtc_state->mode_changed = true;
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if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
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goto next_crtc;
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@ -5382,6 +5388,8 @@ static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
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dc_stream_release(dm_old_crtc_state->stream);
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dm_new_crtc_state->stream = NULL;
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reset_freesync_config_for_crtc(dm_new_crtc_state);
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*lock_and_validation_needed = true;
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} else {/* Add stream for any updated/enabled CRTC */
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@ -5463,7 +5471,9 @@ next_crtc:
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amdgpu_dm_set_ctm(dm_new_crtc_state);
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}
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/* Update Freesync settings. */
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get_freesync_config_for_crtc(dm_new_crtc_state,
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dm_new_conn_state);
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}
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return ret;
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@ -5786,12 +5796,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
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goto fail;
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for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
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struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
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struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
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if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
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!new_crtc_state->color_mgmt_changed &&
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(dm_old_crtc_state->freesync_enabled == dm_new_crtc_state->freesync_enabled))
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!new_crtc_state->vrr_enabled)
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continue;
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if (!new_crtc_state->enable)
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@ -5935,14 +5942,15 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
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struct detailed_data_monitor_range *range;
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struct amdgpu_dm_connector *amdgpu_dm_connector =
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to_amdgpu_dm_connector(connector);
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struct dm_connector_state *dm_con_state;
|
||||
struct dm_connector_state *dm_con_state = NULL;
|
||||
|
||||
struct drm_device *dev = connector->dev;
|
||||
struct amdgpu_device *adev = dev->dev_private;
|
||||
bool freesync_capable = false;
|
||||
|
||||
if (!connector->state) {
|
||||
DRM_ERROR("%s - Connector has no state", __func__);
|
||||
return;
|
||||
goto update;
|
||||
}
|
||||
|
||||
if (!edid) {
|
||||
|
|
@ -5952,9 +5960,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
|
|||
amdgpu_dm_connector->max_vfreq = 0;
|
||||
amdgpu_dm_connector->pixel_clock_mhz = 0;
|
||||
|
||||
dm_con_state->freesync_capable = false;
|
||||
dm_con_state->freesync_enable = false;
|
||||
return;
|
||||
goto update;
|
||||
}
|
||||
|
||||
dm_con_state = to_dm_connector_state(connector->state);
|
||||
|
|
@ -5962,10 +5968,10 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
|
|||
edid_check_required = false;
|
||||
if (!amdgpu_dm_connector->dc_sink) {
|
||||
DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
|
||||
return;
|
||||
goto update;
|
||||
}
|
||||
if (!adev->dm.freesync_module)
|
||||
return;
|
||||
goto update;
|
||||
/*
|
||||
* if edid non zero restrict freesync only for dp and edp
|
||||
*/
|
||||
|
|
@ -5977,7 +5983,6 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
|
|||
amdgpu_dm_connector);
|
||||
}
|
||||
}
|
||||
dm_con_state->freesync_capable = false;
|
||||
if (edid_check_required == true && (edid->version > 1 ||
|
||||
(edid->version == 1 && edid->revision > 1))) {
|
||||
for (i = 0; i < 4; i++) {
|
||||
|
|
@ -6009,8 +6014,16 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
|
|||
if (amdgpu_dm_connector->max_vfreq -
|
||||
amdgpu_dm_connector->min_vfreq > 10) {
|
||||
|
||||
dm_con_state->freesync_capable = true;
|
||||
freesync_capable = true;
|
||||
}
|
||||
}
|
||||
|
||||
update:
|
||||
if (dm_con_state)
|
||||
dm_con_state->freesync_capable = freesync_capable;
|
||||
|
||||
if (connector->vrr_capable_property)
|
||||
drm_connector_set_vrr_capable_property(connector,
|
||||
freesync_capable);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -255,7 +255,11 @@ struct dm_crtc_state {
|
|||
int crc_skip_count;
|
||||
bool crc_enabled;
|
||||
|
||||
bool freesync_enabled;
|
||||
bool freesync_timing_changed;
|
||||
bool freesync_vrr_info_changed;
|
||||
|
||||
bool vrr_supported;
|
||||
struct mod_freesync_config freesync_config;
|
||||
struct dc_crtc_timing_adjust adjust;
|
||||
struct dc_info_packet vrr_infopacket;
|
||||
|
||||
|
|
@ -280,7 +284,6 @@ struct dm_connector_state {
|
|||
uint8_t underscan_hborder;
|
||||
uint8_t max_bpc;
|
||||
bool underscan_enable;
|
||||
bool freesync_enable;
|
||||
bool freesync_capable;
|
||||
uint8_t abm_level;
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue