drm/i915: Write zero to DPLL_MD Reg for non-SDVO output
When the output device is LVDS, maybe the pixel clock of adjusted_mode will be less than that in mode. In such case it will set the incorrect multipler factor in DPLL_MD register. So the dpll_md_reg will be reset when the output type is non-SDVO https://bugs.freedesktop.org/show_bug.cgi?id=22761 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewd-by: Eric Anholt <eric@anholt.net> Signed-off-by: Eric Anholt <eric@anholt.net>
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@ -2652,9 +2652,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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udelay(150);
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if (IS_I965G(dev) && !IS_IGDNG(dev)) {
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sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
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I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
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if (is_sdvo) {
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sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
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I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
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((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
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} else
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I915_WRITE(dpll_md_reg, 0);
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} else {
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/* write it again -- the BIOS does, after all */
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I915_WRITE(dpll_reg, dpll);
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