drm/amd/display: Re-use DCE100 display_power_gating for DCE80
Both functions are the same Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -69,7 +69,7 @@ static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
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******************************************************************************/
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******************************************************************************/
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/***************************PIPE_CONTROL***********************************/
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/***************************PIPE_CONTROL***********************************/
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static bool dce100_enable_display_power_gating(
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bool dce100_enable_display_power_gating(
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struct dc *dc,
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struct dc *dc,
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uint8_t controller_id,
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uint8_t controller_id,
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struct dc_bios *dcb,
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struct dc_bios *dcb,
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@ -38,5 +38,9 @@ void dce100_set_bandwidth(
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struct dc_state *context,
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struct dc_state *context,
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bool decrease_allowed);
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bool decrease_allowed);
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bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,
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struct dc_bios *dcb,
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enum pipe_gating_control power_gating);
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#endif /* __DC_HWSS_DCE100_H__ */
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#endif /* __DC_HWSS_DCE100_H__ */
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@ -70,47 +70,11 @@ static const struct dce80_hw_seq_reg_offsets reg_offsets[] = {
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/***************************PIPE_CONTROL***********************************/
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/***************************PIPE_CONTROL***********************************/
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static bool dce80_enable_display_power_gating(
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struct dc *dc,
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uint8_t controller_id,
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struct dc_bios *dcb,
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enum pipe_gating_control power_gating)
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{
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enum bp_result bp_result = BP_RESULT_OK;
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enum bp_pipe_control_action cntl;
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struct dc_context *ctx = dc->ctx;
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if (power_gating == PIPE_GATING_CONTROL_INIT)
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cntl = ASIC_PIPE_INIT;
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else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
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cntl = ASIC_PIPE_ENABLE;
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else
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cntl = ASIC_PIPE_DISABLE;
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if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){
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bp_result = dcb->funcs->enable_disp_power_gating(
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dcb, controller_id + 1, cntl);
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/* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
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* by default when command table is called
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*/
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dm_write_reg(ctx,
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HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id),
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0);
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}
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if (bp_result == BP_RESULT_OK)
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return true;
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else
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return false;
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}
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void dce80_hw_sequencer_construct(struct dc *dc)
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void dce80_hw_sequencer_construct(struct dc *dc)
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{
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{
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dce110_hw_sequencer_construct(dc);
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dce110_hw_sequencer_construct(dc);
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dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating;
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dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
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dc->hwss.pipe_control_lock = dce_pipe_control_lock;
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dc->hwss.pipe_control_lock = dce_pipe_control_lock;
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dc->hwss.set_bandwidth = dce100_set_bandwidth;
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dc->hwss.set_bandwidth = dce100_set_bandwidth;
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}
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}
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