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ARM: dts: NSP: Add USB3 and USB3 PHY to NSP

This uses the existing Northstar USB3 PHY driver to enable the USB3
ports on NSP.

Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
hifive-unleashed-5.1
Jon Mason 2017-07-31 17:54:23 -04:00 committed by Florian Fainelli
parent 2c5b8512c5
commit bbe526f55b
8 changed files with 75 additions and 0 deletions

View File

@ -302,6 +302,16 @@
#size-cells = <0>;
};
xhci: usb@29000 {
compatible = "generic-xhci";
reg = <0x29000 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb3_phy>;
phy-names = "usb3-phy";
dma-coherent;
status = "disabled";
};
ehci0: usb@2a000 {
compatible = "generic-ehci";
reg = <0x2a000 0x100>;
@ -469,6 +479,15 @@
phy-names = "sata-phy";
};
};
usb3_phy: usb3-phy@104000 {
compatible = "brcm,ns-bx-usb3-phy";
reg = <0x104000 0x1000>,
<0x032000 0x1000>;
reg-names = "dmp", "ccb-mii";
#phy-cells = <0>;
status = "disabled";
};
};
pcie0: pcie@18012000 {

View File

@ -170,3 +170,11 @@
&uart0 {
status = "okay";
};
&usb3_phy {
status = "okay";
};
&xhci {
status = "okay";
};

View File

@ -182,3 +182,11 @@
&uart0 {
status = "okay";
};
&usb3_phy {
status = "okay";
};
&xhci {
status = "okay";
};

View File

@ -202,3 +202,11 @@
&uart0 {
status = "okay";
};
&usb3_phy {
status = "okay";
};
&xhci {
status = "okay";
};

View File

@ -219,3 +219,11 @@
&uart0 {
status = "okay";
};
&usb3_phy {
status = "okay";
};
&xhci {
status = "okay";
};

View File

@ -227,3 +227,11 @@
&uart0 {
status = "okay";
};
&usb3_phy {
status = "okay";
};
&xhci {
status = "okay";
};

View File

@ -229,3 +229,11 @@
&uart0 {
status = "okay";
};
&usb3_phy {
status = "okay";
};
&xhci {
status = "okay";
};

View File

@ -264,3 +264,11 @@
&uart1 {
status = "okay";
};
&usb3_phy {
status = "okay";
};
&xhci {
status = "okay";
};