fsldma: Add DMA_SLAVE support
Use the DMA_SLAVE capability of the DMAEngine API to copy/from a scatterlist into an arbitrary list of hardware address/length pairs. This allows a single DMA transaction to copy data from several different devices into a scatterlist at the same time. This also adds support to enable some controller-specific features such as external start and external pause for a DMA transaction. [dan.j.williams@intel.com: rebased on tx_list movement] Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Acked-by: Li Yang <leoli@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>hifive-unleashed-5.1
Ira Snyder
Dan Williams
parent
e6c7ecb64e
commit
bbea0b6e0d
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@ -0,0 +1,136 @@
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/*
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* Freescale MPC83XX / MPC85XX DMA Controller
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*
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* Copyright (c) 2009 Ira W. Snyder <iws@ovro.caltech.edu>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#ifndef __ARCH_POWERPC_ASM_FSLDMA_H__
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#define __ARCH_POWERPC_ASM_FSLDMA_H__
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#include <linux/dmaengine.h>
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/*
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* Definitions for the Freescale DMA controller's DMA_SLAVE implemention
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*
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* The Freescale DMA_SLAVE implementation was designed to handle many-to-many
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* transfers. An example usage would be an accelerated copy between two
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* scatterlists. Another example use would be an accelerated copy from
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* multiple non-contiguous device buffers into a single scatterlist.
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*
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* A DMA_SLAVE transaction is defined by a struct fsl_dma_slave. This
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* structure contains a list of hardware addresses that should be copied
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* to/from the scatterlist passed into device_prep_slave_sg(). The structure
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* also has some fields to enable hardware-specific features.
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*/
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/**
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* struct fsl_dma_hw_addr
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* @entry: linked list entry
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* @address: the hardware address
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* @length: length to transfer
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*
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* Holds a single physical hardware address / length pair for use
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* with the DMAEngine DMA_SLAVE API.
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*/
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struct fsl_dma_hw_addr {
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struct list_head entry;
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dma_addr_t address;
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size_t length;
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};
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/**
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* struct fsl_dma_slave
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* @addresses: a linked list of struct fsl_dma_hw_addr structures
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* @request_count: value for DMA request count
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* @src_loop_size: setup and enable constant source-address DMA transfers
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* @dst_loop_size: setup and enable constant destination address DMA transfers
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* @external_start: enable externally started DMA transfers
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* @external_pause: enable externally paused DMA transfers
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*
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* Holds a list of address / length pairs for use with the DMAEngine
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* DMA_SLAVE API implementation for the Freescale DMA controller.
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*/
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struct fsl_dma_slave {
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/* List of hardware address/length pairs */
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struct list_head addresses;
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/* Support for extra controller features */
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unsigned int request_count;
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unsigned int src_loop_size;
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unsigned int dst_loop_size;
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bool external_start;
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bool external_pause;
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};
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/**
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* fsl_dma_slave_append - add an address/length pair to a struct fsl_dma_slave
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* @slave: the &struct fsl_dma_slave to add to
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* @address: the hardware address to add
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* @length: the length of bytes to transfer from @address
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*
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* Add a hardware address/length pair to a struct fsl_dma_slave. Returns 0 on
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* success, -ERRNO otherwise.
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*/
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static inline int fsl_dma_slave_append(struct fsl_dma_slave *slave,
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dma_addr_t address, size_t length)
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{
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struct fsl_dma_hw_addr *addr;
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addr = kzalloc(sizeof(*addr), GFP_ATOMIC);
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if (!addr)
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return -ENOMEM;
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INIT_LIST_HEAD(&addr->entry);
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addr->address = address;
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addr->length = length;
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list_add_tail(&addr->entry, &slave->addresses);
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return 0;
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}
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/**
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* fsl_dma_slave_free - free a struct fsl_dma_slave
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* @slave: the struct fsl_dma_slave to free
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*
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* Free a struct fsl_dma_slave and all associated address/length pairs
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*/
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static inline void fsl_dma_slave_free(struct fsl_dma_slave *slave)
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{
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struct fsl_dma_hw_addr *addr, *tmp;
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if (slave) {
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list_for_each_entry_safe(addr, tmp, &slave->addresses, entry) {
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list_del(&addr->entry);
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kfree(addr);
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}
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kfree(slave);
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}
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}
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/**
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* fsl_dma_slave_alloc - allocate a struct fsl_dma_slave
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* @gfp: the flags to pass to kmalloc when allocating this structure
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*
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* Allocate a struct fsl_dma_slave for use by the DMA_SLAVE API. Returns a new
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* struct fsl_dma_slave on success, or NULL on failure.
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*/
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static inline struct fsl_dma_slave *fsl_dma_slave_alloc(gfp_t gfp)
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{
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struct fsl_dma_slave *slave;
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slave = kzalloc(sizeof(*slave), gfp);
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if (!slave)
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return NULL;
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INIT_LIST_HEAD(&slave->addresses);
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return slave;
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}
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#endif /* __ARCH_POWERPC_ASM_FSLDMA_H__ */
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@ -34,6 +34,7 @@
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#include <linux/dmapool.h>
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#include <linux/of_platform.h>
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#include <asm/fsldma.h>
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#include "fsldma.h"
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static void dma_init(struct fsl_dma_chan *fsl_chan)
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@ -551,6 +552,229 @@ fail:
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return NULL;
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}
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/**
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* fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
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* @chan: DMA channel
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* @sgl: scatterlist to transfer to/from
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* @sg_len: number of entries in @scatterlist
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* @direction: DMA direction
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* @flags: DMAEngine flags
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*
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* Prepare a set of descriptors for a DMA_SLAVE transaction. Following the
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* DMA_SLAVE API, this gets the device-specific information from the
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* chan->private variable.
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*/
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static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
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struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
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enum dma_data_direction direction, unsigned long flags)
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{
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struct fsl_dma_chan *fsl_chan;
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struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
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struct fsl_dma_slave *slave;
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struct list_head *tx_list;
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size_t copy;
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int i;
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struct scatterlist *sg;
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size_t sg_used;
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size_t hw_used;
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struct fsl_dma_hw_addr *hw;
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dma_addr_t dma_dst, dma_src;
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if (!chan)
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return NULL;
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if (!chan->private)
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return NULL;
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fsl_chan = to_fsl_chan(chan);
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slave = chan->private;
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if (list_empty(&slave->addresses))
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return NULL;
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hw = list_first_entry(&slave->addresses, struct fsl_dma_hw_addr, entry);
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hw_used = 0;
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/*
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* Build the hardware transaction to copy from the scatterlist to
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* the hardware, or from the hardware to the scatterlist
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*
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* If you are copying from the hardware to the scatterlist and it
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* takes two hardware entries to fill an entire page, then both
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* hardware entries will be coalesced into the same page
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*
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* If you are copying from the scatterlist to the hardware and a
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* single page can fill two hardware entries, then the data will
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* be read out of the page into the first hardware entry, and so on
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*/
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for_each_sg(sgl, sg, sg_len, i) {
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sg_used = 0;
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/* Loop until the entire scatterlist entry is used */
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while (sg_used < sg_dma_len(sg)) {
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/*
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* If we've used up the current hardware address/length
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* pair, we need to load a new one
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*
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* This is done in a while loop so that descriptors with
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* length == 0 will be skipped
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*/
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while (hw_used >= hw->length) {
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/*
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* If the current hardware entry is the last
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* entry in the list, we're finished
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*/
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if (list_is_last(&hw->entry, &slave->addresses))
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goto finished;
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/* Get the next hardware address/length pair */
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hw = list_entry(hw->entry.next,
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struct fsl_dma_hw_addr, entry);
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hw_used = 0;
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}
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/* Allocate the link descriptor from DMA pool */
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new = fsl_dma_alloc_descriptor(fsl_chan);
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if (!new) {
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dev_err(fsl_chan->dev, "No free memory for "
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"link descriptor\n");
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goto fail;
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}
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#ifdef FSL_DMA_LD_DEBUG
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dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new);
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#endif
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/*
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* Calculate the maximum number of bytes to transfer,
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* making sure it is less than the DMA controller limit
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*/
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copy = min_t(size_t, sg_dma_len(sg) - sg_used,
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hw->length - hw_used);
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copy = min_t(size_t, copy, FSL_DMA_BCR_MAX_CNT);
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/*
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* DMA_FROM_DEVICE
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* from the hardware to the scatterlist
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*
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* DMA_TO_DEVICE
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* from the scatterlist to the hardware
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*/
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if (direction == DMA_FROM_DEVICE) {
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dma_src = hw->address + hw_used;
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dma_dst = sg_dma_address(sg) + sg_used;
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} else {
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dma_src = sg_dma_address(sg) + sg_used;
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dma_dst = hw->address + hw_used;
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}
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/* Fill in the descriptor */
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set_desc_cnt(fsl_chan, &new->hw, copy);
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set_desc_src(fsl_chan, &new->hw, dma_src);
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set_desc_dest(fsl_chan, &new->hw, dma_dst);
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/*
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* If this is not the first descriptor, chain the
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* current descriptor after the previous descriptor
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*/
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if (!first) {
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first = new;
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} else {
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set_desc_next(fsl_chan, &prev->hw,
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new->async_tx.phys);
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}
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new->async_tx.cookie = 0;
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async_tx_ack(&new->async_tx);
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prev = new;
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sg_used += copy;
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hw_used += copy;
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/* Insert the link descriptor into the LD ring */
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list_add_tail(&new->node, &first->tx_list);
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}
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}
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finished:
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/* All of the hardware address/length pairs had length == 0 */
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if (!first || !new)
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return NULL;
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new->async_tx.flags = flags;
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new->async_tx.cookie = -EBUSY;
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/* Set End-of-link to the last link descriptor of new list */
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set_ld_eol(fsl_chan, new);
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/* Enable extra controller features */
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if (fsl_chan->set_src_loop_size)
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fsl_chan->set_src_loop_size(fsl_chan, slave->src_loop_size);
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if (fsl_chan->set_dest_loop_size)
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fsl_chan->set_dest_loop_size(fsl_chan, slave->dst_loop_size);
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if (fsl_chan->toggle_ext_start)
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fsl_chan->toggle_ext_start(fsl_chan, slave->external_start);
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if (fsl_chan->toggle_ext_pause)
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fsl_chan->toggle_ext_pause(fsl_chan, slave->external_pause);
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if (fsl_chan->set_request_count)
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fsl_chan->set_request_count(fsl_chan, slave->request_count);
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return &first->async_tx;
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fail:
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/* If first was not set, then we failed to allocate the very first
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* descriptor, and we're done */
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if (!first)
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return NULL;
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/*
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* First is set, so all of the descriptors we allocated have been added
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* to first->tx_list, INCLUDING "first" itself. Therefore we
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* must traverse the list backwards freeing each descriptor in turn
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*
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* We're re-using variables for the loop, oh well
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*/
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tx_list = &first->tx_list;
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list_for_each_entry_safe_reverse(new, prev, tx_list, node) {
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list_del_init(&new->node);
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dma_pool_free(fsl_chan->desc_pool, new, new->async_tx.phys);
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}
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return NULL;
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}
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static void fsl_dma_device_terminate_all(struct dma_chan *chan)
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{
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struct fsl_dma_chan *fsl_chan;
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struct fsl_desc_sw *desc, *tmp;
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unsigned long flags;
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if (!chan)
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return;
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fsl_chan = to_fsl_chan(chan);
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/* Halt the DMA engine */
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dma_halt(fsl_chan);
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spin_lock_irqsave(&fsl_chan->desc_lock, flags);
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/* Remove and free all of the descriptors in the LD queue */
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list_for_each_entry_safe(desc, tmp, &fsl_chan->ld_queue, node) {
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list_del(&desc->node);
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dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
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}
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spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
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}
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/**
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* fsl_dma_update_completed_cookie - Update the completed cookie.
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* @fsl_chan : Freescale DMA channel
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@ -977,12 +1201,15 @@ static int __devinit of_fsl_dma_probe(struct of_device *dev,
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dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
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dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
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dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
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fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
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fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
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fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
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fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
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fdev->common.device_is_tx_complete = fsl_dma_is_complete;
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fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
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fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg;
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fdev->common.device_terminate_all = fsl_dma_device_terminate_all;
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fdev->common.dev = &dev->dev;
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fdev->irq = irq_of_parse_and_map(dev->node, 0);
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