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clk: tegra: pll: Save and restore pll context

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This patch implements save and restore of PLL context.

During system suspend, core power goes off and looses the settings
of the Tegra CAR controller registers.

So during resume, pll context is restored based on cached rate
and state.

Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Sowjanya Komatineni 2019-08-16 12:41:50 -07:00 committed by Thierry Reding
parent fa62228240
commit bc0b3a60fe
1 changed files with 54 additions and 32 deletions
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86
drivers/clk/tegra/clk-pll.c
View file

@ -1008,6 +1008,27 @@ static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
return rate;
}
static void tegra_clk_pll_restore_context(struct clk_hw *hw)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
struct clk_hw *parent = clk_hw_get_parent(hw);
unsigned long parent_rate = clk_hw_get_rate(parent);
unsigned long rate = clk_hw_get_rate(hw);
if (clk_pll_is_enabled(hw))
return;
if (pll->params->set_defaults)
pll->params->set_defaults(pll);
clk_pll_set_rate(hw, rate, parent_rate);
if (!__clk_get_enable_count(hw->clk))
clk_pll_disable(hw);
else
clk_pll_enable(hw);
}
const struct clk_ops tegra_clk_pll_ops = {
.is_enabled = clk_pll_is_enabled,
.enable = clk_pll_enable,
@ -1015,6 +1036,7 @@ const struct clk_ops tegra_clk_pll_ops = {
.recalc_rate = clk_pll_recalc_rate,
.round_rate = clk_pll_round_rate,
.set_rate = clk_pll_set_rate,
.restore_context = tegra_clk_pll_restore_context,
};
const struct clk_ops tegra_clk_plle_ops = {
@ -1802,6 +1824,27 @@ out:
return ret;
}
static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll)
{
u32 val, val_aux;
/* ensure parent is set to pll_ref */
val = pll_readl_base(pll);
val_aux = pll_readl(pll->params->aux_reg, pll);
if (val & PLL_BASE_ENABLE) {
if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
(val_aux & PLLE_AUX_PLLP_SEL))
WARN(1, "pll_e enabled with unsupported parent %s\n",
(val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
"pll_re_vco");
} else {
val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
pll_writel(val_aux, pll->params->aux_reg, pll);
fence_udelay(1, pll->clk_base);
}
}
#endif
static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
@ -2214,27 +2257,12 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
{
struct tegra_clk_pll *pll;
struct clk *clk;
u32 val, val_aux;
pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
if (IS_ERR(pll))
return ERR_CAST(pll);
/* ensure parent is set to pll_re_vco */
val = pll_readl_base(pll);
val_aux = pll_readl(pll_params->aux_reg, pll);
if (val & PLL_BASE_ENABLE) {
if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
(val_aux & PLLE_AUX_PLLP_SEL))
WARN(1, "pll_e enabled with unsupported parent %s\n",
(val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
"pll_re_vco");
} else {
val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
pll_writel(val_aux, pll_params->aux_reg, pll);
}
_clk_plle_tegra_init_parent(pll);
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
&tegra_clk_plle_tegra114_ops);
@ -2276,6 +2304,7 @@ static const struct clk_ops tegra_clk_pllss_ops = {
.recalc_rate = clk_pll_recalc_rate,
.round_rate = clk_pll_ramp_round_rate,
.set_rate = clk_pllxc_set_rate,
.restore_context = tegra_clk_pll_restore_context,
};
struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
@ -2520,11 +2549,19 @@ out:
spin_unlock_irqrestore(pll->lock, flags);
}
static void tegra_clk_plle_t210_restore_context(struct clk_hw *hw)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
_clk_plle_tegra_init_parent(pll);
}
static const struct clk_ops tegra_clk_plle_tegra210_ops = {
.is_enabled = clk_plle_tegra210_is_enabled,
.enable = clk_plle_tegra210_enable,
.disable = clk_plle_tegra210_disable,
.recalc_rate = clk_pll_recalc_rate,
.restore_context = tegra_clk_plle_t210_restore_context,
};
struct clk *tegra_clk_register_plle_tegra210(const char *name,
@ -2535,27 +2572,12 @@ struct clk *tegra_clk_register_plle_tegra210(const char *name,
{
struct tegra_clk_pll *pll;
struct clk *clk;
u32 val, val_aux;
pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
if (IS_ERR(pll))
return ERR_CAST(pll);
/* ensure parent is set to pll_re_vco */
val = pll_readl_base(pll);
val_aux = pll_readl(pll_params->aux_reg, pll);
if (val & PLLE_BASE_ENABLE) {
if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
(val_aux & PLLE_AUX_PLLP_SEL))
WARN(1, "pll_e enabled with unsupported parent %s\n",
(val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
"pll_re_vco");
} else {
val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
pll_writel(val_aux, pll_params->aux_reg, pll);
}
_clk_plle_tegra_init_parent(pll);
clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
&tegra_clk_plle_tegra210_ops);