[ALSA] [Trivial] Fix spaces in gus.h
Modules: GUS Library Fix spaces in gus.h. Signed-off-by: Takashi Iwai <tiwai@suse.de>hifive-unleashed-5.1
Takashi Iwai
Jaroslav Kysela
parent
f739aecced
commit
bc1ff7fc0a
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@ -49,32 +49,32 @@
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#define SNDRV_g_u_s_IRQSTAT (0x226-0x220)
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#define SNDRV_g_u_s_TIMERCNTRL (0x228-0x220)
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#define SNDRV_g_u_s_TIMERDATA (0x229-0x220)
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#define SNDRV_g_u_s_DRAM (0x327-0x220)
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#define SNDRV_g_u_s_DRAM (0x327-0x220)
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#define SNDRV_g_u_s_MIXCNTRLREG (0x220-0x220)
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#define SNDRV_g_u_s_IRQDMACNTRLREG (0x22b-0x220)
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#define SNDRV_g_u_s_REGCNTRLS (0x22f-0x220)
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#define SNDRV_g_u_s_BOARDVERSION (0x726-0x220)
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#define SNDRV_g_u_s_MIXCNTRLPORT (0x726-0x220)
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#define SNDRV_g_u_s_IVER (0x325-0x220)
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#define SNDRV_g_u_s_BOARDVERSION (0x726-0x220)
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#define SNDRV_g_u_s_MIXCNTRLPORT (0x726-0x220)
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#define SNDRV_g_u_s_IVER (0x325-0x220)
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#define SNDRV_g_u_s_MIXDATAPORT (0x326-0x220)
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#define SNDRV_g_u_s_MAXCNTRLPORT (0x326-0x220)
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#define SNDRV_g_u_s_MAXCNTRLPORT (0x326-0x220)
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/* GF1 registers */
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/* global registers */
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#define SNDRV_GF1_GB_ACTIVE_VOICES 0x0e
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#define SNDRV_GF1_GB_VOICES_IRQ 0x0f
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#define SNDRV_GF1_GB_GLOBAL_MODE 0x19
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#define SNDRV_GF1_GB_GLOBAL_MODE 0x19
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#define SNDRV_GF1_GW_LFO_BASE 0x1a
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#define SNDRV_GF1_GB_VOICES_IRQ_READ 0x1f
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#define SNDRV_GF1_GB_DRAM_DMA_CONTROL 0x41
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#define SNDRV_GF1_GW_DRAM_DMA_LOW 0x42
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#define SNDRV_GF1_GW_DRAM_IO_LOW 0x43
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#define SNDRV_GF1_GB_DRAM_IO_HIGH 0x44
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#define SNDRV_GF1_GW_DRAM_DMA_LOW 0x42
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#define SNDRV_GF1_GW_DRAM_IO_LOW 0x43
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#define SNDRV_GF1_GB_DRAM_IO_HIGH 0x44
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#define SNDRV_GF1_GB_SOUND_BLASTER_CONTROL 0x45
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#define SNDRV_GF1_GB_ADLIB_TIMER_1 0x46
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#define SNDRV_GF1_GB_ADLIB_TIMER_2 0x47
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#define SNDRV_GF1_GB_RECORD_RATE 0x48
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#define SNDRV_GF1_GB_RECORD_RATE 0x48
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#define SNDRV_GF1_GB_REC_DMA_CONTROL 0x49
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#define SNDRV_GF1_GB_JOYSTICK_DAC_LEVEL 0x4b
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#define SNDRV_GF1_GB_RESET 0x4c
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@ -83,7 +83,7 @@
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#define SNDRV_GF1_GW_MEMORY_CONFIG 0x52
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#define SNDRV_GF1_GB_MEMORY_CONTROL 0x53
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#define SNDRV_GF1_GW_FIFO_RECORD_BASE_ADDR 0x54
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#define SNDRV_GF1_GW_FIFO_PLAY_BASE_ADDR 0x55
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#define SNDRV_GF1_GW_FIFO_PLAY_BASE_ADDR 0x55
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#define SNDRV_GF1_GW_FIFO_SIZE 0x56
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#define SNDRV_GF1_GW_INTERLEAVE 0x57
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#define SNDRV_GF1_GB_COMPATIBILITY 0x59
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@ -100,39 +100,39 @@
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#define SNDRV_GF1_VA_START SNDRV_GF1_VW_START_HIGH
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#define SNDRV_GF1_VW_END_HIGH 0x04
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#define SNDRV_GF1_VW_END_LOW 0x05
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#define SNDRV_GF1_VA_END SNDRV_GF1_VW_END_HIGH
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#define SNDRV_GF1_VB_VOLUME_RATE 0x06
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#define SNDRV_GF1_VB_VOLUME_START 0x07
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#define SNDRV_GF1_VA_END SNDRV_GF1_VW_END_HIGH
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#define SNDRV_GF1_VB_VOLUME_RATE 0x06
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#define SNDRV_GF1_VB_VOLUME_START 0x07
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#define SNDRV_GF1_VB_VOLUME_END 0x08
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#define SNDRV_GF1_VW_VOLUME 0x09
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#define SNDRV_GF1_VW_CURRENT_HIGH 0x0a
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#define SNDRV_GF1_VW_CURRENT_LOW 0x0b
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#define SNDRV_GF1_VW_CURRENT_HIGH 0x0a
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#define SNDRV_GF1_VW_CURRENT_LOW 0x0b
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#define SNDRV_GF1_VA_CURRENT SNDRV_GF1_VW_CURRENT_HIGH
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#define SNDRV_GF1_VB_PAN 0x0c
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#define SNDRV_GF1_VW_OFFSET_RIGHT 0x0c
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#define SNDRV_GF1_VB_PAN 0x0c
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#define SNDRV_GF1_VW_OFFSET_RIGHT 0x0c
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#define SNDRV_GF1_VB_VOLUME_CONTROL 0x0d
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#define SNDRV_GF1_VB_UPPER_ADDRESS 0x10
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#define SNDRV_GF1_VW_EFFECT_HIGH 0x11
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#define SNDRV_GF1_VW_EFFECT_HIGH 0x11
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#define SNDRV_GF1_VW_EFFECT_LOW 0x12
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#define SNDRV_GF1_VA_EFFECT SNDRV_GF1_VW_EFFECT_HIGH
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#define SNDRV_GF1_VW_OFFSET_LEFT 0x13
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#define SNDRV_GF1_VB_ACCUMULATOR 0x14
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#define SNDRV_GF1_VB_MODE 0x15
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#define SNDRV_GF1_VW_OFFSET_LEFT 0x13
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#define SNDRV_GF1_VB_ACCUMULATOR 0x14
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#define SNDRV_GF1_VB_MODE 0x15
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#define SNDRV_GF1_VW_EFFECT_VOLUME 0x16
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#define SNDRV_GF1_VB_FREQUENCY_LFO 0x17
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#define SNDRV_GF1_VB_VOLUME_LFO 0x18
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#define SNDRV_GF1_VW_OFFSET_RIGHT_FINAL 0x1b
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#define SNDRV_GF1_VW_OFFSET_LEFT_FINAL 0x1c
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#define SNDRV_GF1_VW_EFFECT_VOLUME_FINAL 0x1d
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#define SNDRV_GF1_VW_EFFECT_VOLUME_FINAL 0x1d
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/* ICS registers */
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#define SNDRV_ICS_MIC_DEV 0
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#define SNDRV_ICS_LINE_DEV 1
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#define SNDRV_ICS_LINE_DEV 1
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#define SNDRV_ICS_CD_DEV 2
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#define SNDRV_ICS_GF1_DEV 3
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#define SNDRV_ICS_NONE_DEV 4
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#define SNDRV_ICS_MASTER_DEV 5
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#define SNDRV_ICS_NONE_DEV 4
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#define SNDRV_ICS_MASTER_DEV 5
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/* LFO */
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@ -143,7 +143,7 @@
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#define SNDRV_GF1_DMA_UNSIGNED 0x80
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#define SNDRV_GF1_DMA_16BIT 0x40
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#define SNDRV_GF1_DMA_IRQ 0x20
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#define SNDRV_GF1_DMA_IRQ 0x20
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#define SNDRV_GF1_DMA_WIDTH16 0x04
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#define SNDRV_GF1_DMA_READ 0x02 /* read from GUS's DRAM */
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#define SNDRV_GF1_DMA_ENABLE 0x01
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@ -159,7 +159,7 @@
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/* defines for memory manager */
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#define SNDRV_GF1_MEM_BLOCK_16BIT 0x0001
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#define SNDRV_GF1_MEM_BLOCK_16BIT 0x0001
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#define SNDRV_GF1_MEM_OWNER_DRIVER 0x0001
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#define SNDRV_GF1_MEM_OWNER_WAVE_SIMPLE 0x0002
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@ -169,9 +169,9 @@
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/* constants for interrupt handlers */
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#define SNDRV_GF1_HANDLER_MIDI_OUT 0x00010000
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#define SNDRV_GF1_HANDLER_MIDI_IN 0x00020000
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#define SNDRV_GF1_HANDLER_TIMER1 0x00040000
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#define SNDRV_GF1_HANDLER_TIMER2 0x00080000
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#define SNDRV_GF1_HANDLER_MIDI_IN 0x00020000
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#define SNDRV_GF1_HANDLER_TIMER1 0x00040000
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#define SNDRV_GF1_HANDLER_TIMER2 0x00080000
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#define SNDRV_GF1_HANDLER_VOICE 0x00100000
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#define SNDRV_GF1_HANDLER_DMA_WRITE 0x00200000
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#define SNDRV_GF1_HANDLER_DMA_READ 0x00400000
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