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ARM: dts: sun8i: a23/a33: declare NAND pins 

Declare NAND pins (bus, chip select and ready/busy) for a23/a33 SoCs.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
hifive-unleashed-5.1
Miquel Raynal 2018-04-24 17:55:02 +02:00 committed by Maxime Ripard
parent 9a209c6e95
commit bc3bd041fe
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GPG Key ID: D2B4C094214DAF74
1 changed files with 33 additions and 0 deletions
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33
arch/arm/boot/dts/sun8i-a23-a33.dtsi
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@ -198,6 +198,8 @@
clock-names = "ahb", "mod";
resets = <&ccu RST_BUS_NAND>;
reset-names = "ahb";
pinctrl-names = "default";
pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@ -315,6 +317,37 @@
bias-pull-up;
};
nand_pins: nand-pins {
pins = "PC0", "PC1", "PC2", "PC5",
"PC8", "PC9", "PC10", "PC11",
"PC12", "PC13", "PC14", "PC15";
function = "nand0";
};
nand_pins_cs0: nand-pins-cs0 {
pins = "PC4";
function = "nand0";
bias-pull-up;
};
nand_pins_cs1: nand-pins-cs1 {
pins = "PC3";
function = "nand0";
bias-pull-up;
};
nand_pins_rb0: nand-pins-rb0 {
pins = "PC6";
function = "nand0";
bias-pull-up;
};
nand_pins_rb1: nand-pins-rb1 {
pins = "PC7";
function = "nand0";
bias-pull-up;
};
pwm0_pins: pwm0 {
pins = "PH0";
function = "pwm0";