drm/i915: split get/set pipe timings to timings and src size
Prep work for DSI transcoders. No functional changes. v2: call split functions at a higher level (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/8d67a05eb869a7b0c4ee17c2d3b0b029de34851c.1458313400.git.jani.nikula@intel.com
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@ -96,6 +96,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
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struct drm_i915_gem_object *obj);
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static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
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static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
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static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
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static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
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struct intel_link_m_n *m_n,
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struct intel_link_m_n *m2_n2);
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@ -4827,6 +4828,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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intel_dp_set_m_n(intel_crtc, M1_N1);
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intel_set_pipe_timings(intel_crtc);
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intel_set_pipe_src_size(intel_crtc);
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if (intel_crtc->config->has_pch_encoder) {
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intel_cpu_transcoder_set_m_n(intel_crtc,
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@ -4913,6 +4915,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
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intel_dp_set_m_n(intel_crtc, M1_N1);
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intel_set_pipe_timings(intel_crtc);
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intel_set_pipe_src_size(intel_crtc);
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if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
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I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
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@ -6120,6 +6123,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
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intel_dp_set_m_n(intel_crtc, M1_N1);
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intel_set_pipe_timings(intel_crtc);
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intel_set_pipe_src_size(intel_crtc);
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if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -6192,6 +6196,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
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intel_dp_set_m_n(intel_crtc, M1_N1);
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intel_set_pipe_timings(intel_crtc);
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intel_set_pipe_src_size(intel_crtc);
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i9xx_set_pipeconf(intel_crtc);
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@ -7719,6 +7724,14 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
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(pipe == PIPE_B || pipe == PIPE_C))
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I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
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}
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static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
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{
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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enum pipe pipe = intel_crtc->pipe;
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/* pipesrc controls the size that is scaled from, which should
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* always be the user's requested size.
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*/
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@ -7760,6 +7773,14 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
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pipe_config->base.adjusted_mode.crtc_vtotal += 1;
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pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
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}
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}
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static void intel_get_pipe_src_size(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 tmp;
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tmp = I915_READ(PIPESRC(crtc->pipe));
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pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
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@ -8125,6 +8146,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
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pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
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intel_get_pipe_timings(crtc, pipe_config);
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intel_get_pipe_src_size(crtc, pipe_config);
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i9xx_get_pfit_config(crtc, pipe_config);
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@ -9364,6 +9386,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
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}
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intel_get_pipe_timings(crtc, pipe_config);
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intel_get_pipe_src_size(crtc, pipe_config);
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ironlake_get_pfit_config(crtc, pipe_config);
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@ -9972,6 +9995,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
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haswell_get_ddi_port_state(crtc, pipe_config);
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intel_get_pipe_timings(crtc, pipe_config);
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intel_get_pipe_src_size(crtc, pipe_config);
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if (INTEL_INFO(dev)->gen >= 9) {
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skl_init_scalers(dev, crtc, pipe_config);
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