ARM: dts: omap2 clock data
This patch creates a unique node for each clock in the OMAP2 power, reset and clock manager (PRCM). Signed-off-by: Tero Kristo <t-kristo@ti.com>hifive-unleashed-5.1
Tero Kristo
parent
f7c66b7110
commit
bc797691de
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@ -0,0 +1,270 @@
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/*
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* Device Tree Source for OMAP2420 clock data
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*
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* Copyright (C) 2014 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&prcm_clocks {
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sys_clkout2_src_gate: sys_clkout2_src_gate {
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#clock-cells = <0>;
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compatible = "ti,composite-no-wait-gate-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <15>;
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reg = <0x0070>;
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};
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sys_clkout2_src_mux: sys_clkout2_src_mux {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
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ti,bit-shift = <8>;
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reg = <0x0070>;
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};
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sys_clkout2_src: sys_clkout2_src {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
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};
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sys_clkout2: sys_clkout2 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&sys_clkout2_src>;
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ti,bit-shift = <11>;
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ti,max-div = <64>;
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reg = <0x0070>;
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ti,index-power-of-two;
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};
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dsp_gate_ick: dsp_gate_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-interface-clock";
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clocks = <&dsp_fck>;
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ti,bit-shift = <1>;
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reg = <0x0810>;
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};
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dsp_div_ick: dsp_div_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&dsp_fck>;
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ti,bit-shift = <5>;
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ti,max-div = <3>;
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reg = <0x0840>;
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ti,index-starts-at-one;
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};
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dsp_ick: dsp_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
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};
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iva1_gate_ifck: iva1_gate_ifck {
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#clock-cells = <0>;
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compatible = "ti,composite-gate-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <10>;
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reg = <0x0800>;
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};
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iva1_div_ifck: iva1_div_ifck {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <8>;
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reg = <0x0840>;
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
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};
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iva1_ifck: iva1_ifck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
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};
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iva1_ifck_div: iva1_ifck_div {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&iva1_ifck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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iva1_mpu_int_ifck: iva1_mpu_int_ifck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&iva1_ifck_div>;
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ti,bit-shift = <8>;
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reg = <0x0800>;
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};
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wdt3_ick: wdt3_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l4_ck>;
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ti,bit-shift = <28>;
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reg = <0x0210>;
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};
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wdt3_fck: wdt3_fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&func_32k_ck>;
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ti,bit-shift = <28>;
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reg = <0x0200>;
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};
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mmc_ick: mmc_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l4_ck>;
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ti,bit-shift = <26>;
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reg = <0x0210>;
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};
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mmc_fck: mmc_fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&func_96m_ck>;
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ti,bit-shift = <26>;
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reg = <0x0200>;
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};
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eac_ick: eac_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l4_ck>;
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ti,bit-shift = <24>;
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reg = <0x0210>;
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};
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eac_fck: eac_fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&func_96m_ck>;
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ti,bit-shift = <24>;
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reg = <0x0200>;
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};
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i2c1_fck: i2c1_fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&func_12m_ck>;
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ti,bit-shift = <19>;
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reg = <0x0200>;
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};
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i2c2_fck: i2c2_fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&func_12m_ck>;
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ti,bit-shift = <20>;
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reg = <0x0200>;
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};
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vlynq_ick: vlynq_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&core_l3_ck>;
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ti,bit-shift = <3>;
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reg = <0x0210>;
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};
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vlynq_gate_fck: vlynq_gate_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-gate-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <3>;
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reg = <0x0200>;
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};
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core_d18_ck: core_d18_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&core_ck>;
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clock-mult = <1>;
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clock-div = <18>;
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};
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vlynq_mux_fck: vlynq_mux_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;
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ti,bit-shift = <15>;
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reg = <0x0240>;
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};
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vlynq_fck: vlynq_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>;
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};
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};
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&prcm_clockdomains {
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gfx_clkdm: gfx_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&gfx_ick>;
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};
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core_l3_clkdm: core_l3_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>;
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};
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wkup_clkdm: wkup_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
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<&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
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<&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>;
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};
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iva1_clkdm: iva1_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&iva1_mpu_int_ifck>;
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};
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dss_clkdm: dss_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&dss_ick>, <&dss_54m_fck>;
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};
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core_l4_clkdm: core_l4_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
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<&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
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<&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
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<&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>,
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<&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
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<&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>,
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<&uart3_ick>, <&uart3_fck>, <&cam_ick>,
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<&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>,
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<&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>,
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<&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>,
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<&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>,
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<&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>,
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<&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
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<&pka_ick>;
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};
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};
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&func_96m_ck {
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compatible = "fixed-factor-clock";
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clocks = <&apll96_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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&dsp_div_fck {
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
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};
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&ssi_ssr_sst_div_fck {
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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};
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@ -14,6 +14,32 @@
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compatible = "ti,omap2420", "ti,omap2";
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ocp {
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prcm: prcm@48008000 {
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compatible = "ti,omap2-prcm";
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reg = <0x48008000 0x1000>;
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prcm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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prcm_clockdomains: clockdomains {
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};
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};
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scrm: scrm@48000000 {
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compatible = "ti,omap2-scrm";
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reg = <0x48000000 0x1000>;
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scrm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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scrm_clockdomains: clockdomains {
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};
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};
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counter32k: counter@48004000 {
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compatible = "ti,omap-counter32k";
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reg = <0x48004000 0x20>;
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@ -148,3 +174,6 @@
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&i2c2 {
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compatible = "ti,omap2420-i2c";
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};
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/include/ "omap24xx-clocks.dtsi"
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/include/ "omap2420-clocks.dtsi"
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@ -0,0 +1,344 @@
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/*
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* Device Tree Source for OMAP2430 clock data
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*
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* Copyright (C) 2014 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&scrm_clocks {
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mcbsp3_mux_fck: mcbsp3_mux_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&func_96m_ck>, <&mcbsp_clks>;
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reg = <0x02e8>;
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};
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mcbsp3_fck: mcbsp3_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
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};
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mcbsp4_mux_fck: mcbsp4_mux_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&func_96m_ck>, <&mcbsp_clks>;
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ti,bit-shift = <2>;
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reg = <0x02e8>;
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};
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mcbsp4_fck: mcbsp4_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
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};
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mcbsp5_mux_fck: mcbsp5_mux_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&func_96m_ck>, <&mcbsp_clks>;
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ti,bit-shift = <4>;
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reg = <0x02e8>;
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};
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mcbsp5_fck: mcbsp5_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
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};
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};
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&prcm_clocks {
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iva2_1_gate_ick: iva2_1_gate_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-gate-clock";
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clocks = <&dsp_fck>;
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ti,bit-shift = <0>;
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reg = <0x0800>;
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};
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iva2_1_div_ick: iva2_1_div_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&dsp_fck>;
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ti,bit-shift = <5>;
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ti,max-div = <3>;
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reg = <0x0840>;
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ti,index-starts-at-one;
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};
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iva2_1_ick: iva2_1_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
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};
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mdm_gate_ick: mdm_gate_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-interface-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <0>;
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reg = <0x0c10>;
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};
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mdm_div_ick: mdm_div_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&core_ck>;
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reg = <0x0c40>;
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ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>;
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};
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mdm_ick: mdm_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&mdm_gate_ick>, <&mdm_div_ick>;
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};
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mdm_osc_ck: mdm_osc_ck {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&osc_ck>;
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ti,bit-shift = <1>;
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reg = <0x0c00>;
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};
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mcbsp3_ick: mcbsp3_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l4_ck>;
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ti,bit-shift = <3>;
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reg = <0x0214>;
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};
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mcbsp3_gate_fck: mcbsp3_gate_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-gate-clock";
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clocks = <&mcbsp_clks>;
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ti,bit-shift = <3>;
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reg = <0x0204>;
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};
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mcbsp4_ick: mcbsp4_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l4_ck>;
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ti,bit-shift = <4>;
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reg = <0x0214>;
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};
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||||
mcbsp4_gate_fck: mcbsp4_gate_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-gate-clock";
|
||||
clocks = <&mcbsp_clks>;
|
||||
ti,bit-shift = <4>;
|
||||
reg = <0x0204>;
|
||||
};
|
||||
|
||||
mcbsp5_ick: mcbsp5_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&l4_ck>;
|
||||
ti,bit-shift = <5>;
|
||||
reg = <0x0214>;
|
||||
};
|
||||
|
||||
mcbsp5_gate_fck: mcbsp5_gate_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-gate-clock";
|
||||
clocks = <&mcbsp_clks>;
|
||||
ti,bit-shift = <5>;
|
||||
reg = <0x0204>;
|
||||
};
|
||||
|
||||
mcspi3_ick: mcspi3_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&l4_ck>;
|
||||
ti,bit-shift = <9>;
|
||||
reg = <0x0214>;
|
||||
};
|
||||
|
||||
mcspi3_fck: mcspi3_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&func_48m_ck>;
|
||||
ti,bit-shift = <9>;
|
||||
reg = <0x0204>;
|
||||
};
|
||||
|
||||
icr_ick: icr_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&sys_ck>;
|
||||
ti,bit-shift = <6>;
|
||||
reg = <0x0410>;
|
||||
};
|
||||
|
||||
i2chs1_fck: i2chs1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap2430-interface-clock";
|
||||
clocks = <&func_96m_ck>;
|
||||
ti,bit-shift = <19>;
|
||||
reg = <0x0204>;
|
||||
};
|
||||
|
||||
i2chs2_fck: i2chs2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap2430-interface-clock";
|
||||
clocks = <&func_96m_ck>;
|
||||
ti,bit-shift = <20>;
|
||||
reg = <0x0204>;
|
||||
};
|
||||
|
||||
usbhs_ick: usbhs_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l3_ck>;
|
||||
ti,bit-shift = <6>;
|
||||
reg = <0x0214>;
|
||||
};
|
||||
|
||||
mmchs1_ick: mmchs1_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&l4_ck>;
|
||||
ti,bit-shift = <7>;
|
||||
reg = <0x0214>;
|
||||
};
|
||||
|
||||
mmchs1_fck: mmchs1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&func_96m_ck>;
|
||||
ti,bit-shift = <7>;
|
||||
reg = <0x0204>;
|
||||
};
|
||||
|
||||
mmchs2_ick: mmchs2_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&l4_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x0214>;
|
||||
};
|
||||
|
||||
mmchs2_fck: mmchs2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&func_96m_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x0204>;
|
||||
};
|
||||
|
||||
gpio5_ick: gpio5_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&l4_ck>;
|
||||
ti,bit-shift = <10>;
|
||||
reg = <0x0214>;
|
||||
};
|
||||
|
||||
gpio5_fck: gpio5_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&func_32k_ck>;
|
||||
ti,bit-shift = <10>;
|
||||
reg = <0x0204>;
|
||||
};
|
||||
|
||||
mdm_intc_ick: mdm_intc_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&l4_ck>;
|
||||
ti,bit-shift = <11>;
|
||||
reg = <0x0214>;
|
||||
};
|
||||
|
||||
mmchsdb1_fck: mmchsdb1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&func_32k_ck>;
|
||||
ti,bit-shift = <16>;
|
||||
reg = <0x0204>;
|
||||
};
|
||||
|
||||
mmchsdb2_fck: mmchsdb2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&func_32k_ck>;
|
||||
ti,bit-shift = <17>;
|
||||
reg = <0x0204>;
|
||||
};
|
||||
};
|
||||
|
||||
&prcm_clockdomains {
|
||||
gfx_clkdm: gfx_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&gfx_ick>;
|
||||
};
|
||||
|
||||
core_l3_clkdm: core_l3_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>;
|
||||
};
|
||||
|
||||
wkup_clkdm: wkup_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
|
||||
<&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
|
||||
<&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>,
|
||||
<&icr_ick>;
|
||||
};
|
||||
|
||||
dss_clkdm: dss_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&dss_ick>, <&dss_54m_fck>;
|
||||
};
|
||||
|
||||
core_l4_clkdm: core_l4_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
|
||||
<&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
|
||||
<&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
|
||||
<&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
|
||||
<&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>,
|
||||
<&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
|
||||
<&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>,
|
||||
<&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>,
|
||||
<&uart3_fck>, <&cam_ick>, <&mailboxes_ick>,
|
||||
<&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>,
|
||||
<&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>,
|
||||
<&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>,
|
||||
<&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
|
||||
<&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>,
|
||||
<&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>,
|
||||
<&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>,
|
||||
<&mmchsdb2_fck>;
|
||||
};
|
||||
|
||||
mdm_clkdm: mdm_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&mdm_osc_ck>;
|
||||
};
|
||||
};
|
||||
|
||||
&func_96m_ck {
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&apll96_ck>, <&alt_ck>;
|
||||
ti,bit-shift = <4>;
|
||||
reg = <0x0540>;
|
||||
};
|
||||
|
||||
&dsp_div_fck {
|
||||
ti,max-div = <4>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
&ssi_ssr_sst_div_fck {
|
||||
ti,max-div = <5>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
|
@ -14,6 +14,32 @@
|
|||
compatible = "ti,omap2430", "ti,omap2";
|
||||
|
||||
ocp {
|
||||
prcm: prcm@49006000 {
|
||||
compatible = "ti,omap2-prcm";
|
||||
reg = <0x49006000 0x1000>;
|
||||
|
||||
prcm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
prcm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
scrm: scrm@49002000 {
|
||||
compatible = "ti,omap2-scrm";
|
||||
reg = <0x49002000 0x1000>;
|
||||
|
||||
scrm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
scrm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
counter32k: counter@49020000 {
|
||||
compatible = "ti,omap-counter32k";
|
||||
reg = <0x49020000 0x20>;
|
||||
|
|
@ -255,3 +281,6 @@
|
|||
&i2c2 {
|
||||
compatible = "ti,omap2430-i2c";
|
||||
};
|
||||
|
||||
/include/ "omap24xx-clocks.dtsi"
|
||||
/include/ "omap2430-clocks.dtsi"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue