Blackfin arch: update to latest anomaly sheets
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
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include/asm-blackfin/mach-bf527/anomaly.h
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include/asm-blackfin/mach-bf527/anomaly.h
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/*
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* File: include/asm-blackfin/mach-bf527/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (C) 2004-2007 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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/* This file shoule be up to date with:
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* - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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#define ANOMALY_05000119 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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#define ANOMALY_05000265 (1)
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/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
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#define ANOMALY_05000301 (1)
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/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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#define ANOMALY_05000312 (1)
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/* Incorrect Access of OTP_STATUS During otp_write() Function */
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#define ANOMALY_05000328 (1)
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/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
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#define ANOMALY_05000337 (1)
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/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */
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#define ANOMALY_05000342 (1)
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/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
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#define ANOMALY_05000347 (1)
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#endif
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@ -44,8 +44,6 @@
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#define ANOMALY_05000122 (1)
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/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
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#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
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/* PPI Data Lengths Between 8 and 16 do not zero out upper bits*/
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#define ANOMALY_05000166 (1) /* XXX: deleted from BF537 sheet ? */
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/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
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#define ANOMALY_05000180 (1)
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/* Instruction Cache Is Not Functional */
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@ -7,7 +7,7 @@
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*/
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/* This file shoule be up to date with:
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* - Revision B, April 6, 2007; ADSP-BF549 Silicon Anomaly List
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* - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define ANOMALY_05000122 (1)
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/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
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#define ANOMALY_05000255 (1)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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#define ANOMALY_05000265 (1)
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/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
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#define ANOMALY_05000272 (1)
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/* False Hardware Error Exception when ISR context is not restored */
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#define ANOMALY_05000281 (1)
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/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
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#define ANOMALY_05000304 (1)
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_05000310 (1)
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/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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#define ANOMALY_05000337 (1)
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/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
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#define ANOMALY_05000338 (1)
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/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
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#define ANOMALY_05000340 (1)
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/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
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#define ANOMALY_05000344 (1)
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/* USB Calibration Value Is Not Intialized */
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#define ANOMALY_05000346 (1)
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/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
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#define ANOMALY_05000347 (1)
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/* Data Lost when Core Reads SDH Data FIFO */
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#define ANOMALY_05000349 (1)
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/* PLL Status Register Is Inaccurate */
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#define ANOMALY_05000351 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000125 (0)
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#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000158 (0)
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#define ANOMALY_05000183 (0)
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000311 (0)
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