perf tools: Add Intel PT support for PSB periods
The PSB packet is a synchronization packet that provides a starting point for decoding or recovery from errors. This patch adds support for a new Intel PT feature that allows the frequency of PSB packets to be specified. Support for this feature is indicated by /sys/bus/event_source/devices/intel_pt/caps/psb_cyc which contains "1" if the feature is supported and "0" otherwise. The PSB period can be specified as a PMU config term e.g. perf record -e intel_pt/psb_period=2/u sleep 1 The default value is 3 or the nearest lower value that is supported. 0 is always supported. Valid values are given by: /sys/bus/event_source/devices/intel_pt/caps/psb_periods which contains a hexadecimal value, the bits of which represent valid values e.g. bit 2 set means value 2 is valid. The value is converted to the approximate number of trace bytes between PSB packets as: 2 ^ (value + 11) e.g. value 3 means 16KiB bytes between PSBs If an invalid value is entered, the error message will give a list of valid values e.g. $ perf record -e intel_pt/psb_period=15/u uname Invalid psb_period for intel_pt. Valid values are: 0-5 tools/perf/Documentation/intel-pt.txt is updated in a later patch as there are a number of new features being added. For more information about PSB periods refer to the Intel 64 and IA-32 Architectures SDM Chapter 36 Intel Processor Trace from June 2015 or later. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Link: http://lkml.kernel.org/r/1437150840-31811-18-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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@ -99,17 +99,121 @@ static int intel_pt_parse_terms(struct list_head *formats, const char *str,
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return intel_pt_parse_terms_with_default(formats, str, config);
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}
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static size_t intel_pt_psb_period(struct perf_pmu *intel_pt_pmu __maybe_unused,
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struct perf_evlist *evlist __maybe_unused)
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static u64 intel_pt_masked_bits(u64 mask, u64 bits)
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{
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return 256;
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const u64 top_bit = 1ULL << 63;
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u64 res = 0;
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int i;
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for (i = 0; i < 64; i++) {
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if (mask & top_bit) {
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res <<= 1;
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if (bits & top_bit)
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res |= 1;
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}
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mask <<= 1;
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bits <<= 1;
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}
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return res;
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}
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static int intel_pt_read_config(struct perf_pmu *intel_pt_pmu, const char *str,
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struct perf_evlist *evlist, u64 *res)
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{
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struct perf_evsel *evsel;
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u64 mask;
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*res = 0;
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mask = perf_pmu__format_bits(&intel_pt_pmu->format, str);
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if (!mask)
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return -EINVAL;
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evlist__for_each(evlist, evsel) {
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if (evsel->attr.type == intel_pt_pmu->type) {
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*res = intel_pt_masked_bits(mask, evsel->attr.config);
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return 0;
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}
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}
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return -EINVAL;
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}
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static size_t intel_pt_psb_period(struct perf_pmu *intel_pt_pmu,
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struct perf_evlist *evlist)
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{
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u64 val;
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int err, topa_multiple_entries;
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size_t psb_period;
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if (perf_pmu__scan_file(intel_pt_pmu, "caps/topa_multiple_entries",
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"%d", &topa_multiple_entries) != 1)
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topa_multiple_entries = 0;
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/*
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* Use caps/topa_multiple_entries to indicate early hardware that had
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* extra frequent PSBs.
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*/
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if (!topa_multiple_entries) {
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psb_period = 256;
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goto out;
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}
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err = intel_pt_read_config(intel_pt_pmu, "psb_period", evlist, &val);
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if (err)
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val = 0;
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psb_period = 1 << (val + 11);
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out:
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pr_debug2("%s psb_period %zu\n", intel_pt_pmu->name, psb_period);
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return psb_period;
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}
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static int intel_pt_pick_bit(int bits, int target)
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{
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int pos, pick = -1;
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for (pos = 0; bits; bits >>= 1, pos++) {
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if (bits & 1) {
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if (pos <= target || pick < 0)
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pick = pos;
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if (pos >= target)
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break;
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}
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}
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return pick;
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}
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static u64 intel_pt_default_config(struct perf_pmu *intel_pt_pmu)
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{
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char buf[256];
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int psb_cyc, psb_periods, psb_period;
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int pos = 0;
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u64 config;
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intel_pt_parse_terms(&intel_pt_pmu->format, "tsc", &config);
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pos += scnprintf(buf + pos, sizeof(buf) - pos, "tsc");
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if (perf_pmu__scan_file(intel_pt_pmu, "caps/psb_cyc", "%d",
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&psb_cyc) != 1)
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psb_cyc = 1;
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if (psb_cyc) {
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if (perf_pmu__scan_file(intel_pt_pmu, "caps/psb_periods", "%x",
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&psb_periods) != 1)
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psb_periods = 0;
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if (psb_periods) {
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psb_period = intel_pt_pick_bit(psb_periods, 3);
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pos += scnprintf(buf + pos, sizeof(buf) - pos,
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",psb_period=%d", psb_period);
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}
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}
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pr_debug2("%s default config: %s\n", intel_pt_pmu->name, buf);
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intel_pt_parse_terms(&intel_pt_pmu->format, buf, &config);
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return config;
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}
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@ -239,6 +343,103 @@ static int intel_pt_track_switches(struct perf_evlist *evlist)
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return 0;
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}
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static void intel_pt_valid_str(char *str, size_t len, u64 valid)
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{
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unsigned int val, last = 0, state = 1;
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int p = 0;
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str[0] = '\0';
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for (val = 0; val <= 64; val++, valid >>= 1) {
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if (valid & 1) {
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last = val;
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switch (state) {
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case 0:
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p += scnprintf(str + p, len - p, ",");
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/* Fall through */
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case 1:
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p += scnprintf(str + p, len - p, "%u", val);
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state = 2;
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break;
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case 2:
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state = 3;
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break;
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case 3:
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state = 4;
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break;
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default:
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break;
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}
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} else {
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switch (state) {
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case 3:
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p += scnprintf(str + p, len - p, ",%u", last);
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state = 0;
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break;
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case 4:
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p += scnprintf(str + p, len - p, "-%u", last);
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state = 0;
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break;
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default:
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break;
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}
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if (state != 1)
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state = 0;
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}
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}
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}
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static int intel_pt_val_config_term(struct perf_pmu *intel_pt_pmu,
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const char *caps, const char *name,
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const char *supported, u64 config)
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{
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char valid_str[256];
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unsigned int shift;
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unsigned long long valid;
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u64 bits;
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int ok;
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if (perf_pmu__scan_file(intel_pt_pmu, caps, "%llx", &valid) != 1)
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valid = 0;
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if (supported &&
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perf_pmu__scan_file(intel_pt_pmu, supported, "%d", &ok) == 1 && !ok)
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valid = 0;
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valid |= 1;
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bits = perf_pmu__format_bits(&intel_pt_pmu->format, name);
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config &= bits;
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for (shift = 0; bits && !(bits & 1); shift++)
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bits >>= 1;
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config >>= shift;
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if (config > 63)
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goto out_err;
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if (valid & (1 << config))
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return 0;
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out_err:
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intel_pt_valid_str(valid_str, sizeof(valid_str), valid);
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pr_err("Invalid %s for %s. Valid values are: %s\n",
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name, INTEL_PT_PMU_NAME, valid_str);
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return -EINVAL;
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}
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static int intel_pt_validate_config(struct perf_pmu *intel_pt_pmu,
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struct perf_evsel *evsel)
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{
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if (!evsel)
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return 0;
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return intel_pt_val_config_term(intel_pt_pmu, "caps/psb_periods",
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"psb_period", "caps/psb_cyc",
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evsel->attr.config);
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}
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static int intel_pt_recording_options(struct auxtrace_record *itr,
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struct perf_evlist *evlist,
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struct record_opts *opts)
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@ -251,6 +452,7 @@ static int intel_pt_recording_options(struct auxtrace_record *itr,
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const struct cpu_map *cpus = evlist->cpus;
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bool privileged = geteuid() == 0 || perf_event_paranoid() < 0;
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u64 tsc_bit;
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int err;
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ptr->evlist = evlist;
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ptr->snapshot_mode = opts->auxtrace_snapshot_mode;
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if (!opts->full_auxtrace)
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return 0;
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err = intel_pt_validate_config(intel_pt_pmu, intel_pt_evsel);
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if (err)
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return err;
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/* Set default sizes for snapshot mode */
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if (opts->auxtrace_snapshot_mode) {
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size_t psb_period = intel_pt_psb_period(intel_pt_pmu, evlist);
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* threads.
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*/
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if (have_timing_info && !cpu_map__empty(cpus)) {
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int err;
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err = intel_pt_track_switches(evlist);
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if (err == -EPERM)
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pr_debug2("Unable to select sched:sched_switch\n");
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/* Add dummy event to keep tracking */
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if (opts->full_auxtrace) {
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struct perf_evsel *tracking_evsel;
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int err;
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err = parse_events(evlist, "dummy:u", NULL);
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if (err)
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