serial: 8250_dw: Use 64-bit access for OCTEON.
Although the existing code appears to work on most hardware, the hardware designers tell us that 8-bit access to the registers is not guaranteed to be reliable. Also the OCTEON simulation environments prohibit 8-bit accesses. For these reasons, we use __raw_readq/__raw_writeq for OCTEON. This code is protected with #ifdef CONFIG_64BIT so it still builds under configurations lacking readq/writeq. We can get rid of the #ifdef __BIG_ENDIAN, as under 64-bit accesses, OCTEON is byte order invariant. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -122,13 +122,44 @@ static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
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return dw8250_modify_msr(p, offset, value);
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}
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/* Read Back (rb) version to ensure register access ording. */
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static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value)
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#ifdef CONFIG_64BIT
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static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
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{
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dw8250_serial_out(p, offset, value);
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dw8250_serial_in(p, UART_LCR);
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unsigned int value;
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value = (u8)__raw_readq(p->membase + (offset << p->regshift));
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return dw8250_modify_msr(p, offset, value);
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}
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static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = p->private_data;
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if (offset == UART_MCR)
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d->last_mcr = value;
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value &= 0xff;
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__raw_writeq(value, p->membase + (offset << p->regshift));
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/* Read back to ensure register write ordering. */
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__raw_readq(p->membase + (UART_LCR << p->regshift));
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/* Make sure LCR write wasn't ignored */
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if (offset == UART_LCR) {
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int tries = 1000;
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while (tries--) {
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unsigned int lcr = p->serial_in(p, UART_LCR);
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if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
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return;
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dw8250_force_idle(p);
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__raw_writeq(value & 0xff,
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p->membase + (UART_LCR << p->regshift));
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}
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dev_err(p->dev, "Couldn't set LCR to %d\n", value);
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}
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}
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#endif /* CONFIG_64BIT */
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static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = p->private_data;
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@ -260,21 +291,17 @@ static int dw8250_probe_of(struct uart_port *p,
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bool has_ucv = true;
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int id;
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#ifdef CONFIG_64BIT
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if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
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#ifdef __BIG_ENDIAN
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/*
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* Low order bits of these 64-bit registers, when
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* accessed as a byte, are 7 bytes further down in the
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* address space in big endian mode.
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*/
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p->membase += 7;
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#endif
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p->serial_out = dw8250_serial_out_rb;
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p->serial_in = dw8250_serial_inq;
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p->serial_out = dw8250_serial_outq;
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p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
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p->type = PORT_OCTEON;
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data->usr_reg = 0x27;
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has_ucv = false;
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} else if (!of_property_read_u32(np, "reg-io-width", &val)) {
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} else
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#endif
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if (!of_property_read_u32(np, "reg-io-width", &val)) {
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switch (val) {
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case 1:
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break;
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