[ARM] msm: clean up iomap and devices
- Add some more peripherals (sdcc, etc) to the iomap. - Remove virtual base addresses for devices that we should be passing physical addresses to drivers via resources and ioremap()ing. - don't try to use uarts for ll debug once the mmu is enabled due to problems with the peripheral window - make base addresses void __iomem * and fixup irq.c and timer.c - Remove common.c and bring in devices.c/devices.h similar to the PXA architecture. Signed-off-by: Brian Swetland <swetland@google.com>
This commit is contained in:
parent
b8a16e1fdf
commit
bcc0f6af07
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@ -1,8 +1,6 @@
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obj-y += io.o idle.o irq.o timer.o dma.o
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obj-y += devices.o
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obj-y += proc_comm.o
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# Common code for board init
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obj-y += common.o
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obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o
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@ -33,6 +33,8 @@
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include "devices.h"
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static struct resource smc91x_resources[] = {
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[0] = {
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.start = 0x9C004300,
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@ -53,31 +55,12 @@ static struct platform_device smc91x_device = {
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.resource = smc91x_resources,
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};
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static void mddi0_panel_power(int on)
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{
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}
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static struct msm_mddi_platform_data msm_mddi0_pdata = {
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.panel_power = mddi0_panel_power,
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.has_vsync_irq = 0,
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};
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static struct platform_device msm_mddi0_device = {
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.name = "msm_mddi",
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.id = 0,
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.dev = {
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.platform_data = &msm_mddi0_pdata
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},
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};
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static struct platform_device msm_serial0_device = {
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.name = "msm_serial",
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.id = 0,
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};
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static struct platform_device *devices[] __initdata = {
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&msm_serial0_device,
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&msm_mddi0_device,
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&msm_device_uart3,
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&msm_device_smd,
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&msm_device_nand,
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&msm_device_hsusb,
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&msm_device_i2c,
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&smc91x_device,
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};
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@ -91,7 +74,6 @@ static void __init halibut_init_irq(void)
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static void __init halibut_init(void)
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{
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platform_add_devices(devices, ARRAY_SIZE(devices));
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msm_add_devices();
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}
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static void __init halibut_map_io(void)
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@ -100,11 +82,6 @@ static void __init halibut_map_io(void)
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}
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MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
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/* UART for LL DEBUG */
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.phys_io = MSM_UART1_PHYS,
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.io_pg_offst = ((MSM_UART1_BASE) >> 18) & 0xfffc,
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.boot_params = 0x10000100,
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.map_io = halibut_map_io,
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.init_irq = halibut_init_irq,
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@ -1,116 +0,0 @@
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/* linux/arch/arm/mach-msm/common.c
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*
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* Common setup code for MSM7K Boards
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*
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* Copyright (C) 2007 Google, Inc.
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* Author: Brian Swetland <swetland@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <asm/mach/flash.h>
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#include <asm/setup.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <mach/msm_iomap.h>
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#include <mach/board.h>
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struct flash_platform_data msm_nand_data = {
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.parts = 0,
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.nr_parts = 0,
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};
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static struct resource msm_nand_resources[] = {
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[0] = {
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.start = 7,
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.end = 7,
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.flags = IORESOURCE_DMA,
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},
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};
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static struct platform_device msm_nand_device = {
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.name = "msm_nand",
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.id = -1,
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.num_resources = ARRAY_SIZE(msm_nand_resources),
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.resource = msm_nand_resources,
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.dev = {
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.platform_data = &msm_nand_data,
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},
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};
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static struct platform_device msm_smd_device = {
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.name = "msm_smd",
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.id = -1,
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};
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static struct resource msm_i2c_resources[] = {
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{
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.start = MSM_I2C_BASE,
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.end = MSM_I2C_BASE + MSM_I2C_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = INT_PWB_I2C,
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.end = INT_PWB_I2C,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device msm_i2c_device = {
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.name = "msm_i2c",
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.id = 0,
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.num_resources = ARRAY_SIZE(msm_i2c_resources),
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.resource = msm_i2c_resources,
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};
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static struct resource usb_resources[] = {
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{
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.start = MSM_HSUSB_PHYS,
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.end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = INT_USB_HS,
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.end = INT_USB_HS,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device msm_hsusb_device = {
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.name = "msm_hsusb",
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.id = -1,
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.num_resources = ARRAY_SIZE(usb_resources),
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.resource = usb_resources,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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};
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static struct platform_device *devices[] __initdata = {
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&msm_nand_device,
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&msm_smd_device,
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&msm_i2c_device,
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&msm_hsusb_device,
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};
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void __init msm_add_devices(void)
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{
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platform_add_devices(devices, ARRAY_SIZE(devices));
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}
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267
arch/arm/mach-msm/devices.c
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267
arch/arm/mach-msm/devices.c
Normal file
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@ -0,0 +1,267 @@
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/* linux/arch/arm/mach-msm/devices.c
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*
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* Copyright (C) 2008 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <mach/msm_iomap.h>
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#include "devices.h"
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#include <asm/mach/flash.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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static struct resource resources_uart1[] = {
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{
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.start = INT_UART1,
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.end = INT_UART1,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = MSM_UART1_PHYS,
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.end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource resources_uart2[] = {
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{
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.start = INT_UART2,
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.end = INT_UART2,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = MSM_UART2_PHYS,
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.end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource resources_uart3[] = {
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{
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.start = INT_UART3,
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.end = INT_UART3,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = MSM_UART3_PHYS,
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.end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device msm_device_uart1 = {
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.name = "msm_serial",
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.id = 0,
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.num_resources = ARRAY_SIZE(resources_uart1),
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.resource = resources_uart1,
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};
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struct platform_device msm_device_uart2 = {
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.name = "msm_serial",
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.id = 1,
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.num_resources = ARRAY_SIZE(resources_uart2),
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.resource = resources_uart2,
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};
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struct platform_device msm_device_uart3 = {
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.name = "msm_serial",
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.id = 2,
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.num_resources = ARRAY_SIZE(resources_uart3),
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.resource = resources_uart3,
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};
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static struct resource resources_i2c[] = {
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{
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.start = MSM_I2C_PHYS,
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.end = MSM_I2C_PHYS + MSM_I2C_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = INT_PWB_I2C,
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.end = INT_PWB_I2C,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device msm_device_i2c = {
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.name = "msm_i2c",
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.id = 0,
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.num_resources = ARRAY_SIZE(resources_i2c),
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.resource = resources_i2c,
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};
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static struct resource resources_hsusb[] = {
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{
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.start = MSM_HSUSB_PHYS,
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.end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = INT_USB_HS,
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.end = INT_USB_HS,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device msm_device_hsusb = {
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.name = "msm_hsusb",
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.id = -1,
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.num_resources = ARRAY_SIZE(resources_hsusb),
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.resource = resources_hsusb,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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};
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struct flash_platform_data msm_nand_data = {
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.parts = NULL,
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.nr_parts = 0,
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};
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static struct resource resources_nand[] = {
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[0] = {
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.start = 7,
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.end = 7,
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.flags = IORESOURCE_DMA,
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},
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};
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struct platform_device msm_device_nand = {
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.name = "msm_nand",
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.id = -1,
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.num_resources = ARRAY_SIZE(resources_nand),
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.resource = resources_nand,
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.dev = {
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.platform_data = &msm_nand_data,
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},
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};
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struct platform_device msm_device_smd = {
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.name = "msm_smd",
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.id = -1,
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};
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static struct resource resources_sdc1[] = {
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{
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.start = MSM_SDC1_PHYS,
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.end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = INT_SDC1_0,
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.end = INT_SDC1_1,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = 8,
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.end = 8,
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.flags = IORESOURCE_DMA,
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},
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};
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static struct resource resources_sdc2[] = {
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{
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.start = MSM_SDC2_PHYS,
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.end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = INT_SDC2_0,
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.end = INT_SDC2_1,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = 8,
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.end = 8,
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.flags = IORESOURCE_DMA,
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},
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};
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static struct resource resources_sdc3[] = {
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{
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.start = MSM_SDC3_PHYS,
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.end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = INT_SDC3_0,
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.end = INT_SDC3_1,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = 8,
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.end = 8,
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.flags = IORESOURCE_DMA,
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},
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};
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static struct resource resources_sdc4[] = {
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{
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.start = MSM_SDC4_PHYS,
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.end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = INT_SDC4_0,
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.end = INT_SDC4_1,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = 8,
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.end = 8,
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.flags = IORESOURCE_DMA,
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},
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};
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struct platform_device msm_device_sdc1 = {
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.name = "msm_sdcc",
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.id = 1,
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.num_resources = ARRAY_SIZE(resources_sdc1),
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.resource = resources_sdc1,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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};
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struct platform_device msm_device_sdc2 = {
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.name = "msm_sdcc",
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.id = 2,
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.num_resources = ARRAY_SIZE(resources_sdc2),
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.resource = resources_sdc2,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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};
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struct platform_device msm_device_sdc3 = {
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.name = "msm_sdcc",
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.id = 3,
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.num_resources = ARRAY_SIZE(resources_sdc3),
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.resource = resources_sdc3,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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};
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struct platform_device msm_device_sdc4 = {
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.name = "msm_sdcc",
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.id = 4,
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.num_resources = ARRAY_SIZE(resources_sdc4),
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.resource = resources_sdc4,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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};
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36
arch/arm/mach-msm/devices.h
Normal file
36
arch/arm/mach-msm/devices.h
Normal file
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@ -0,0 +1,36 @@
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/* linux/arch/arm/mach-msm/devices.h
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*
|
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* Copyright (C) 2008 Google, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
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|
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#ifndef __ARCH_ARM_MACH_MSM_DEVICES_H
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#define __ARCH_ARM_MACH_MSM_DEVICES_H
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extern struct platform_device msm_device_uart1;
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extern struct platform_device msm_device_uart2;
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extern struct platform_device msm_device_uart3;
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extern struct platform_device msm_device_sdc1;
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extern struct platform_device msm_device_sdc2;
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extern struct platform_device msm_device_sdc3;
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extern struct platform_device msm_device_sdc4;
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extern struct platform_device msm_device_hsusb;
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extern struct platform_device msm_device_i2c;
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extern struct platform_device msm_device_smd;
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|
||||
extern struct platform_device msm_device_nand;
|
||||
|
||||
#endif
|
|
@ -22,18 +22,22 @@
|
|||
mrc p15, 0, \rx, c1, c0
|
||||
tst \rx, #1
|
||||
ldreq \rx, =MSM_UART1_PHYS
|
||||
ldrne \rx, =MSM_UART1_BASE
|
||||
movne \rx, #0
|
||||
.endm
|
||||
|
||||
.macro senduart,rd,rx
|
||||
str \rd, [\rx, #0x0C]
|
||||
teq \rx, #0
|
||||
strne \rd, [\rx, #0x0C]
|
||||
.endm
|
||||
|
||||
.macro waituart,rd,rx
|
||||
@ wait for TX_READY
|
||||
teq \rx, #0
|
||||
bne 2f
|
||||
1: ldr \rd, [\rx, #0x08]
|
||||
tst \rd, #0x04
|
||||
beq 1b
|
||||
2:
|
||||
.endm
|
||||
|
||||
.macro busyuart,rd,rx
|
||||
|
|
|
@ -37,11 +37,17 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#define MSM_VIC_BASE 0xE0000000
|
||||
#ifdef __ASSEMBLY__
|
||||
#define IOMEM(x) x
|
||||
#else
|
||||
#define IOMEM(x) ((void __force __iomem *)(x))
|
||||
#endif
|
||||
|
||||
#define MSM_VIC_BASE IOMEM(0xE0000000)
|
||||
#define MSM_VIC_PHYS 0xC0000000
|
||||
#define MSM_VIC_SIZE SZ_4K
|
||||
|
||||
#define MSM_CSR_BASE 0xE0001000
|
||||
#define MSM_CSR_BASE IOMEM(0xE0001000)
|
||||
#define MSM_CSR_PHYS 0xC0100000
|
||||
#define MSM_CSR_SIZE SZ_4K
|
||||
|
||||
|
@ -49,56 +55,67 @@
|
|||
#define MSM_GPT_BASE MSM_CSR_BASE
|
||||
#define MSM_GPT_SIZE SZ_4K
|
||||
|
||||
#define MSM_DMOV_BASE 0xE0002000
|
||||
#define MSM_DMOV_BASE IOMEM(0xE0002000)
|
||||
#define MSM_DMOV_PHYS 0xA9700000
|
||||
#define MSM_DMOV_SIZE SZ_4K
|
||||
|
||||
#define MSM_UART1_BASE 0xE0003000
|
||||
#define MSM_UART1_PHYS 0xA9A00000
|
||||
#define MSM_UART1_SIZE SZ_4K
|
||||
|
||||
#define MSM_UART2_BASE 0xE0004000
|
||||
#define MSM_UART2_PHYS 0xA9B00000
|
||||
#define MSM_UART2_SIZE SZ_4K
|
||||
|
||||
#define MSM_UART3_BASE 0xE0005000
|
||||
#define MSM_UART3_PHYS 0xA9C00000
|
||||
#define MSM_UART3_SIZE SZ_4K
|
||||
|
||||
#define MSM_I2C_BASE 0xE0006000
|
||||
#define MSM_I2C_PHYS 0xA9900000
|
||||
#define MSM_I2C_SIZE SZ_4K
|
||||
|
||||
#define MSM_GPIO1_BASE 0xE0007000
|
||||
#define MSM_GPIO1_BASE IOMEM(0xE0003000)
|
||||
#define MSM_GPIO1_PHYS 0xA9200000
|
||||
#define MSM_GPIO1_SIZE SZ_4K
|
||||
|
||||
#define MSM_GPIO2_BASE 0xE0008000
|
||||
#define MSM_GPIO2_BASE IOMEM(0xE0004000)
|
||||
#define MSM_GPIO2_PHYS 0xA9300000
|
||||
#define MSM_GPIO2_SIZE SZ_4K
|
||||
|
||||
#define MSM_HSUSB_BASE 0xE0009000
|
||||
#define MSM_HSUSB_PHYS 0xA0800000
|
||||
#define MSM_HSUSB_SIZE SZ_4K
|
||||
|
||||
#define MSM_CLK_CTL_BASE 0xE000A000
|
||||
#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
|
||||
#define MSM_CLK_CTL_PHYS 0xA8600000
|
||||
#define MSM_CLK_CTL_SIZE SZ_4K
|
||||
|
||||
#define MSM_PMDH_BASE 0xE000B000
|
||||
#define MSM_PMDH_PHYS 0xAA600000
|
||||
#define MSM_PMDH_SIZE SZ_4K
|
||||
|
||||
#define MSM_EMDH_BASE 0xE000C000
|
||||
#define MSM_EMDH_PHYS 0xAA700000
|
||||
#define MSM_EMDH_SIZE SZ_4K
|
||||
|
||||
#define MSM_MDP_BASE 0xE0010000
|
||||
#define MSM_MDP_PHYS 0xAA200000
|
||||
#define MSM_MDP_SIZE 0x000F0000
|
||||
|
||||
#define MSM_SHARED_RAM_BASE 0xE0100000
|
||||
#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
|
||||
#define MSM_SHARED_RAM_PHYS 0x01F00000
|
||||
#define MSM_SHARED_RAM_SIZE SZ_1M
|
||||
|
||||
#define MSM_UART1_PHYS 0xA9A00000
|
||||
#define MSM_UART1_SIZE SZ_4K
|
||||
|
||||
#define MSM_UART2_PHYS 0xA9B00000
|
||||
#define MSM_UART2_SIZE SZ_4K
|
||||
|
||||
#define MSM_UART3_PHYS 0xA9C00000
|
||||
#define MSM_UART3_SIZE SZ_4K
|
||||
|
||||
#define MSM_SDC1_PHYS 0xA0400000
|
||||
#define MSM_SDC1_SIZE SZ_4K
|
||||
|
||||
#define MSM_SDC2_PHYS 0xA0500000
|
||||
#define MSM_SDC2_SIZE SZ_4K
|
||||
|
||||
#define MSM_SDC3_PHYS 0xA0600000
|
||||
#define MSM_SDC3_SIZE SZ_4K
|
||||
|
||||
#define MSM_SDC4_PHYS 0xA0700000
|
||||
#define MSM_SDC4_SIZE SZ_4K
|
||||
|
||||
#define MSM_I2C_PHYS 0xA9900000
|
||||
#define MSM_I2C_SIZE SZ_4K
|
||||
|
||||
#define MSM_HSUSB_PHYS 0xA0800000
|
||||
#define MSM_HSUSB_SIZE SZ_4K
|
||||
|
||||
#define MSM_PMDH_PHYS 0xAA600000
|
||||
#define MSM_PMDH_SIZE SZ_4K
|
||||
|
||||
#define MSM_EMDH_PHYS 0xAA700000
|
||||
#define MSM_EMDH_SIZE SZ_4K
|
||||
|
||||
#define MSM_MDP_PHYS 0xAA200000
|
||||
#define MSM_MDP_SIZE 0x000F0000
|
||||
|
||||
#define MSM_MDC_PHYS 0xAA500000
|
||||
#define MSM_MDC_SIZE SZ_1M
|
||||
|
||||
#define MSM_AD5_PHYS 0xAC000000
|
||||
#define MSM_AD5_SIZE (SZ_1M*13)
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
@ -28,7 +28,7 @@
|
|||
#include <mach/board.h>
|
||||
|
||||
#define MSM_DEVICE(name) { \
|
||||
.virtual = MSM_##name##_BASE, \
|
||||
.virtual = (unsigned long) MSM_##name##_BASE, \
|
||||
.pfn = __phys_to_pfn(MSM_##name##_PHYS), \
|
||||
.length = MSM_##name##_SIZE, \
|
||||
.type = MT_DEVICE_NONSHARED, \
|
||||
|
@ -39,19 +39,11 @@ static struct map_desc msm_io_desc[] __initdata = {
|
|||
MSM_DEVICE(CSR),
|
||||
MSM_DEVICE(GPT),
|
||||
MSM_DEVICE(DMOV),
|
||||
MSM_DEVICE(UART1),
|
||||
MSM_DEVICE(UART2),
|
||||
MSM_DEVICE(UART3),
|
||||
MSM_DEVICE(I2C),
|
||||
MSM_DEVICE(GPIO1),
|
||||
MSM_DEVICE(GPIO2),
|
||||
MSM_DEVICE(HSUSB),
|
||||
MSM_DEVICE(CLK_CTL),
|
||||
MSM_DEVICE(PMDH),
|
||||
MSM_DEVICE(EMDH),
|
||||
MSM_DEVICE(MDP),
|
||||
{
|
||||
.virtual = MSM_SHARED_RAM_BASE,
|
||||
.virtual = (unsigned long) MSM_SHARED_RAM_BASE,
|
||||
.pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
|
||||
.length = MSM_SHARED_RAM_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
|
|
|
@ -66,20 +66,20 @@
|
|||
|
||||
static void msm_irq_ack(unsigned int irq)
|
||||
{
|
||||
unsigned reg = VIC_INT_CLEAR0 + ((irq & 32) ? 4 : 0);
|
||||
void __iomem *reg = VIC_INT_CLEAR0 + ((irq & 32) ? 4 : 0);
|
||||
irq = 1 << (irq & 31);
|
||||
writel(irq, reg);
|
||||
}
|
||||
|
||||
static void msm_irq_mask(unsigned int irq)
|
||||
{
|
||||
unsigned reg = VIC_INT_ENCLEAR0 + ((irq & 32) ? 4 : 0);
|
||||
void __iomem *reg = VIC_INT_ENCLEAR0 + ((irq & 32) ? 4 : 0);
|
||||
writel(1 << (irq & 31), reg);
|
||||
}
|
||||
|
||||
static void msm_irq_unmask(unsigned int irq)
|
||||
{
|
||||
unsigned reg = VIC_INT_ENSET0 + ((irq & 32) ? 4 : 0);
|
||||
void __iomem *reg = VIC_INT_ENSET0 + ((irq & 32) ? 4 : 0);
|
||||
writel(1 << (irq & 31), reg);
|
||||
}
|
||||
|
||||
|
@ -90,8 +90,8 @@ static int msm_irq_set_wake(unsigned int irq, unsigned int on)
|
|||
|
||||
static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
|
||||
{
|
||||
unsigned treg = VIC_INT_TYPE0 + ((irq & 32) ? 4 : 0);
|
||||
unsigned preg = VIC_INT_POLARITY0 + ((irq & 32) ? 4 : 0);
|
||||
void __iomem *treg = VIC_INT_TYPE0 + ((irq & 32) ? 4 : 0);
|
||||
void __iomem *preg = VIC_INT_POLARITY0 + ((irq & 32) ? 4 : 0);
|
||||
int b = 1 << (irq & 31);
|
||||
|
||||
if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
|
||||
|
|
|
@ -45,7 +45,7 @@ struct msm_clock {
|
|||
struct clock_event_device clockevent;
|
||||
struct clocksource clocksource;
|
||||
struct irqaction irq;
|
||||
uint32_t regbase;
|
||||
void __iomem *regbase;
|
||||
uint32_t freq;
|
||||
uint32_t shift;
|
||||
};
|
||||
|
|
Loading…
Reference in a new issue