Merge branch 'pci/host-rockchip' into next
* pci/host-rockchip: PCI: rockchip: Set vendor ID from local core config space PCI: rockchip: Fix rockchip_pcie_probe() error path to free resource list PCI: rockchip: Mark PM functions as __maybe_unused PCI: rockchip: Use readl_poll_timeout() instead of open-coding it PCI: rockchip: Disable RC's ASPM L0s based on DT "aspm-no-l0s" PCI: rockchip: Add system PM support
This commit is contained in:
Bjorn Helgaas
commit
bcea623c65
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@ -43,6 +43,8 @@ Required properties:
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- interrupt-map-mask and interrupt-map: standard PCI properties
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Optional Property:
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- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
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using 24MHz OSC for RC's PHY.
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- ep-gpios: contain the entry for pre-reset gpio
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- num-lanes: number of lanes to use
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- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
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@ -20,6 +20,7 @@
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#include <linux/gpio/consumer.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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@ -55,6 +56,10 @@
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#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
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#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
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#define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
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#define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c)
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#define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0)
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#define PCIE_CLIENT_DEBUG_LTSSM_L1 0x18
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#define PCIE_CLIENT_DEBUG_LTSSM_L2 0x19
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#define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48)
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#define PCIE_CLIENT_LINK_STATUS_UP 0x00300000
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#define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000
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@ -120,6 +125,7 @@
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#define PCIE_CORE_INT_CT BIT(11)
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#define PCIE_CORE_INT_UTC BIT(18)
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#define PCIE_CORE_INT_MMVC BIT(19)
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#define PCIE_CORE_CONFIG_VENDOR (PCIE_CORE_CTRL_MGMT_BASE + 0x44)
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#define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210)
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#define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300)
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@ -133,13 +139,14 @@
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PCIE_CORE_INT_MMVC)
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#define PCIE_RC_CONFIG_BASE 0xa00000
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#define PCIE_RC_CONFIG_VENDOR (PCIE_RC_CONFIG_BASE + 0x00)
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#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
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#define PCIE_RC_CONFIG_SCC_SHIFT 16
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#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
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#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
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#define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff
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#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
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#define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc)
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#define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10)
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#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
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#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
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#define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
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@ -167,9 +174,11 @@
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#define IB_ROOT_PORT_REG_SIZE_SHIFT 3
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#define AXI_WRAPPER_IO_WRITE 0x6
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#define AXI_WRAPPER_MEM_WRITE 0x2
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#define AXI_WRAPPER_NOR_MSG 0xc
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#define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
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#define MIN_AXI_ADDR_BITS_PASSED 8
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#define PCIE_RC_SEND_PME_OFF 0x11960
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#define ROCKCHIP_VENDOR_ID 0x1d87
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#define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20)
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#define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15)
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@ -178,6 +187,12 @@
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#define PCIE_ECAM_ADDR(bus, dev, func, reg) \
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(PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
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PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
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#define PCIE_LINK_IS_L2(x) \
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(((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2)
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#define PCIE_LINK_UP(x) \
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(((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
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#define PCIE_LINK_IS_GEN2(x) \
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(((x) & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G)
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#define RC_REGION_0_ADDR_TRANS_H 0x00000000
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#define RC_REGION_0_ADDR_TRANS_L 0x00000000
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@ -211,7 +226,9 @@ struct rockchip_pcie {
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u32 io_size;
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int offset;
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phys_addr_t io_bus_addr;
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void __iomem *msg_region;
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u32 mem_size;
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phys_addr_t msg_bus_addr;
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phys_addr_t mem_bus_addr;
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};
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@ -449,7 +466,6 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
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struct device *dev = rockchip->dev;
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int err;
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u32 status;
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unsigned long timeout;
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gpiod_set_value(rockchip->ep_gpio, 0);
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@ -590,23 +606,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
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gpiod_set_value(rockchip->ep_gpio, 1);
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/* 500ms timeout value should be enough for Gen1/2 training */
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timeout = jiffies + msecs_to_jiffies(500);
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for (;;) {
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status = rockchip_pcie_read(rockchip,
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PCIE_CLIENT_BASIC_STATUS1);
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if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
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PCIE_CLIENT_LINK_STATUS_UP) {
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dev_dbg(dev, "PCIe link training gen1 pass!\n");
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break;
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}
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if (time_after(jiffies, timeout)) {
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dev_err(dev, "PCIe link training gen1 timeout!\n");
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return -ETIMEDOUT;
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}
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msleep(20);
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err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
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status, PCIE_LINK_UP(status), 20,
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500 * USEC_PER_MSEC);
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if (err) {
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dev_err(dev, "PCIe link training gen1 timeout!\n");
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return -ETIMEDOUT;
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}
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if (rockchip->link_gen == 2) {
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@ -618,22 +623,11 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
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status |= PCI_EXP_LNKCTL_RL;
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rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
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timeout = jiffies + msecs_to_jiffies(500);
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for (;;) {
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status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
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if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
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PCIE_CORE_PL_CONF_SPEED_5G) {
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dev_dbg(dev, "PCIe link training gen2 pass!\n");
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break;
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}
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if (time_after(jiffies, timeout)) {
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dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
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break;
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}
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msleep(20);
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}
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err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,
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status, PCIE_LINK_IS_GEN2(status), 20,
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500 * USEC_PER_MSEC);
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if (err)
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dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
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}
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/* Check the final link width from negotiated lane counter from MGMT */
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@ -643,7 +637,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
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dev_dbg(dev, "current link width is x%d\n", status);
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rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
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PCIE_RC_CONFIG_VENDOR);
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PCIE_CORE_CONFIG_VENDOR);
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rockchip_pcie_write(rockchip,
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PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
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PCIE_RC_CONFIG_RID_CCR);
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@ -653,6 +647,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
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status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
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rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
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/* Clear L0s from RC's link cap */
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if (of_property_read_bool(dev->of_node, "aspm-no-l0s")) {
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status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP);
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status &= ~PCIE_RC_CONFIG_LINK_CAP_L0S;
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rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP);
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}
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rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
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rockchip_pcie_write(rockchip,
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@ -1186,6 +1187,85 @@ static int rockchip_cfg_atu(struct rockchip_pcie *rockchip)
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}
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}
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/* assign message regions */
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rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1 + offset,
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AXI_WRAPPER_NOR_MSG,
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20 - 1, 0, 0);
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rockchip->msg_bus_addr = rockchip->mem_bus_addr +
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((reg_no + offset) << 20);
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return err;
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}
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static int rockchip_pcie_wait_l2(struct rockchip_pcie *rockchip)
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{
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u32 value;
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int err;
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/* send PME_TURN_OFF message */
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writel(0x0, rockchip->msg_region + PCIE_RC_SEND_PME_OFF);
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/* read LTSSM and wait for falling into L2 link state */
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err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_DEBUG_OUT_0,
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value, PCIE_LINK_IS_L2(value), 20,
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jiffies_to_usecs(5 * HZ));
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if (err) {
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dev_err(rockchip->dev, "PCIe link enter L2 timeout!\n");
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return err;
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}
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return 0;
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}
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static int __maybe_unused rockchip_pcie_suspend_noirq(struct device *dev)
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{
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struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
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int ret;
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/* disable core and cli int since we don't need to ack PME_ACK */
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rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) |
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PCIE_CLIENT_INT_CLI, PCIE_CLIENT_INT_MASK);
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rockchip_pcie_write(rockchip, (u32)PCIE_CORE_INT, PCIE_CORE_INT_MASK);
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ret = rockchip_pcie_wait_l2(rockchip);
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if (ret) {
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rockchip_pcie_enable_interrupts(rockchip);
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return ret;
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}
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phy_power_off(rockchip->phy);
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phy_exit(rockchip->phy);
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clk_disable_unprepare(rockchip->clk_pcie_pm);
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clk_disable_unprepare(rockchip->hclk_pcie);
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clk_disable_unprepare(rockchip->aclk_perf_pcie);
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clk_disable_unprepare(rockchip->aclk_pcie);
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return ret;
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}
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static int __maybe_unused rockchip_pcie_resume_noirq(struct device *dev)
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{
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struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
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int err;
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clk_prepare_enable(rockchip->clk_pcie_pm);
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clk_prepare_enable(rockchip->hclk_pcie);
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clk_prepare_enable(rockchip->aclk_perf_pcie);
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clk_prepare_enable(rockchip->aclk_pcie);
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err = rockchip_pcie_init_port(rockchip);
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if (err)
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return err;
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err = rockchip_cfg_atu(rockchip);
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if (err)
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return err;
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/* Need this to enter L1 again */
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rockchip_pcie_update_txcredit_mui(rockchip);
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rockchip_pcie_enable_interrupts(rockchip);
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return 0;
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}
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@ -1209,6 +1289,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
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if (!rockchip)
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return -ENOMEM;
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platform_set_drvdata(pdev, rockchip);
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rockchip->dev = dev;
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err = rockchip_pcie_parse_dt(rockchip);
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@ -1262,7 +1343,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
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err = devm_request_pci_bus_resources(dev, &res);
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if (err)
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goto err_vpcie;
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goto err_free_res;
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/* Get the I/O and memory ranges from DT */
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resource_list_for_each_entry(win, &res) {
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@ -1295,11 +1376,19 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
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err = rockchip_cfg_atu(rockchip);
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if (err)
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goto err_vpcie;
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goto err_free_res;
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rockchip->msg_region = devm_ioremap(rockchip->dev,
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rockchip->msg_bus_addr, SZ_1M);
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if (!rockchip->msg_region) {
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err = -ENOMEM;
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goto err_free_res;
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}
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bus = pci_scan_root_bus(&pdev->dev, 0, &rockchip_pcie_ops, rockchip, &res);
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if (!bus) {
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err = -ENOMEM;
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goto err_vpcie;
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goto err_free_res;
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}
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pci_bus_size_bridges(bus);
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@ -1310,6 +1399,8 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
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pci_bus_add_devices(bus);
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return err;
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err_free_res:
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pci_free_resource_list(&res);
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err_vpcie:
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if (!IS_ERR(rockchip->vpcie3v3))
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regulator_disable(rockchip->vpcie3v3);
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@ -1329,6 +1420,11 @@ err_aclk_pcie:
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return err;
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}
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static const struct dev_pm_ops rockchip_pcie_pm_ops = {
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_pcie_suspend_noirq,
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rockchip_pcie_resume_noirq)
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};
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static const struct of_device_id rockchip_pcie_of_match[] = {
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{ .compatible = "rockchip,rk3399-pcie", },
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{}
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@ -1338,6 +1434,7 @@ static struct platform_driver rockchip_pcie_driver = {
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.driver = {
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.name = "rockchip-pcie",
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.of_match_table = rockchip_pcie_of_match,
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.pm = &rockchip_pcie_pm_ops,
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},
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.probe = rockchip_pcie_probe,
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Reference in a new issue