ARM: SAMSUNG: Convert irq-uart to generic irq chip
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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@ -27,60 +27,6 @@
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/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
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* are consecutive when looking up the interrupt in the demux routines.
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*/
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static inline void __iomem *s3c_irq_uart_base(struct irq_data *data)
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{
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struct s3c_uart_irq *uirq = irq_data_get_irq_chip_data(data);
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return uirq->regs;
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}
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static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
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{
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return irq & 3;
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}
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static void s3c_irq_uart_mask(struct irq_data *data)
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{
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void __iomem *regs = s3c_irq_uart_base(data);
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unsigned int bit = s3c_irq_uart_bit(data->irq);
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u32 reg;
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reg = __raw_readl(regs + S3C64XX_UINTM);
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reg |= (1 << bit);
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__raw_writel(reg, regs + S3C64XX_UINTM);
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}
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static void s3c_irq_uart_maskack(struct irq_data *data)
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{
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void __iomem *regs = s3c_irq_uart_base(data);
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unsigned int bit = s3c_irq_uart_bit(data->irq);
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u32 reg;
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reg = __raw_readl(regs + S3C64XX_UINTM);
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reg |= (1 << bit);
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__raw_writel(reg, regs + S3C64XX_UINTM);
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__raw_writel(1 << bit, regs + S3C64XX_UINTP);
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}
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static void s3c_irq_uart_unmask(struct irq_data *data)
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{
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void __iomem *regs = s3c_irq_uart_base(data);
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unsigned int bit = s3c_irq_uart_bit(data->irq);
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u32 reg;
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reg = __raw_readl(regs + S3C64XX_UINTM);
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reg &= ~(1 << bit);
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__raw_writel(reg, regs + S3C64XX_UINTM);
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}
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static void s3c_irq_uart_ack(struct irq_data *data)
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{
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void __iomem *regs = s3c_irq_uart_base(data);
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unsigned int bit = s3c_irq_uart_bit(data->irq);
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__raw_writel(1 << bit, regs + S3C64XX_UINTP);
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}
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static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
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{
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struct s3c_uart_irq *uirq = desc->irq_data.handler_data;
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@ -97,30 +43,25 @@ static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
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generic_handle_irq(base + 3);
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}
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static struct irq_chip s3c_irq_uart = {
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.name = "s3c-uart",
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.irq_mask = s3c_irq_uart_mask,
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.irq_unmask = s3c_irq_uart_unmask,
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.irq_mask_ack = s3c_irq_uart_maskack,
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.irq_ack = s3c_irq_uart_ack,
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};
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static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
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{
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void __iomem *reg_base = uirq->regs;
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unsigned int irq;
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int offs;
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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/* mask all interrupts at the start. */
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__raw_writel(0xf, reg_base + S3C64XX_UINTM);
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for (offs = 0; offs < 3; offs++) {
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irq = uirq->base_irq + offs;
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irq_set_chip_and_handler(irq, &s3c_irq_uart, handle_level_irq);
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irq_set_chip_data(irq, uirq);
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set_irq_flags(irq, IRQF_VALID);
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}
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gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base,
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handle_level_irq);
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ct = gc->chip_types;
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ct->chip.irq_ack = irq_gc_ack;
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ct->chip.irq_mask = irq_gc_mask_set_bit;
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ct->chip.irq_unmask = irq_gc_mask_clr_bit;
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ct->regs.ack = S3C64XX_UINTP;
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ct->regs.mask = S3C64XX_UINTM;
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irq_setup_generic_chip(gc, IRQ_MSK(4), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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irq_set_handler_data(uirq->parent_irq, uirq);
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irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
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