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drm/i915: factor out is_always_on_domain 

It is just cleaner this way and makes it easier to add support for
other HW generations with always-on power wells powering a different
set of domains.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
hifive-unleashed-5.1
Imre Deak 2013-10-16 17:25:49 +03:00 committed by Daniel Vetter
parent f52e353e19
commit bddc76452d
2 changed files with 38 additions and 54 deletions
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8
drivers/gpu/drm/i915/i915_drv.h
View File

@ -100,8 +100,12 @@ enum intel_display_power_domain {
POWER_DOMAIN_TRANSCODER_C,
POWER_DOMAIN_TRANSCODER_EDP,
POWER_DOMAIN_VGA,
POWER_DOMAIN_NUM,
};
#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
@ -109,6 +113,10 @@ enum intel_display_power_domain {
((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
(tran) + POWER_DOMAIN_TRANSCODER_A)
#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PIPE_A) | \
BIT(POWER_DOMAIN_TRANSCODER_EDP))
enum hpd_pin {
HPD_NONE = 0,
HPD_PORT_A = HPD_NONE, /* PORT_A is internal */

84
drivers/gpu/drm/i915/intel_pm.c
View File

@ -5517,6 +5517,23 @@ void intel_suspend_hw(struct drm_device *dev)
lpt_suspend_hw(dev);
}
static bool is_always_on_power_domain(struct drm_device *dev,
enum intel_display_power_domain domain)
{
unsigned long always_on_domains;
BUG_ON(BIT(domain) & ~POWER_DOMAIN_MASK);
if (IS_HASWELL(dev)) {
always_on_domains = HSW_ALWAYS_ON_POWER_DOMAINS;
} else {
WARN_ON(1);
return true;
}
return BIT(domain) & always_on_domains;
}
/**
* We should only use the power well if we explicitly asked the hardware to
* enable it, so check if it's enabled and also check if we've requested it to
@ -5530,24 +5547,11 @@ bool intel_display_power_enabled(struct drm_device *dev,
if (!HAS_POWER_WELL(dev))
return true;
switch (domain) {
case POWER_DOMAIN_PIPE_A:
case POWER_DOMAIN_TRANSCODER_EDP:
if (is_always_on_power_domain(dev, domain))
return true;
case POWER_DOMAIN_VGA:
case POWER_DOMAIN_PIPE_B:
case POWER_DOMAIN_PIPE_C:
case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
case POWER_DOMAIN_TRANSCODER_A:
case POWER_DOMAIN_TRANSCODER_B:
case POWER_DOMAIN_TRANSCODER_C:
return I915_READ(HSW_PWR_WELL_DRIVER) ==
return I915_READ(HSW_PWR_WELL_DRIVER) ==
(HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
default:
BUG();
}
}
static void __intel_set_power_well(struct drm_device *dev, bool enable)
@ -5619,26 +5623,12 @@ void intel_display_power_get(struct drm_device *dev,
if (!HAS_POWER_WELL(dev))
return;
switch (domain) {
case POWER_DOMAIN_PIPE_A:
case POWER_DOMAIN_TRANSCODER_EDP:
if (is_always_on_power_domain(dev, domain))
return;
case POWER_DOMAIN_VGA:
case POWER_DOMAIN_PIPE_B:
case POWER_DOMAIN_PIPE_C:
case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
case POWER_DOMAIN_TRANSCODER_A:
case POWER_DOMAIN_TRANSCODER_B:
case POWER_DOMAIN_TRANSCODER_C:
spin_lock_irq(&power_well->lock);
__intel_power_well_get(power_well);
spin_unlock_irq(&power_well->lock);
return;
default:
BUG();
}
spin_lock_irq(&power_well->lock);
__intel_power_well_get(power_well);
spin_unlock_irq(&power_well->lock);
}
void intel_display_power_put(struct drm_device *dev,
@ -5650,26 +5640,12 @@ void intel_display_power_put(struct drm_device *dev,
if (!HAS_POWER_WELL(dev))
return;
switch (domain) {
case POWER_DOMAIN_PIPE_A:
case POWER_DOMAIN_TRANSCODER_EDP:
if (is_always_on_power_domain(dev, domain))
return;
case POWER_DOMAIN_VGA:
case POWER_DOMAIN_PIPE_B:
case POWER_DOMAIN_PIPE_C:
case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
case POWER_DOMAIN_TRANSCODER_A:
case POWER_DOMAIN_TRANSCODER_B:
case POWER_DOMAIN_TRANSCODER_C:
spin_lock_irq(&power_well->lock);
__intel_power_well_put(power_well);
spin_unlock_irq(&power_well->lock);
return;
default:
BUG();
}
spin_lock_irq(&power_well->lock);
__intel_power_well_put(power_well);
spin_unlock_irq(&power_well->lock);
}
static struct i915_power_well *hsw_pwr;