m68knommu: use MCF_IRQ_PIT1 instead of MCFINT_VECBASE + MCFINT_PIT1
use MCF_IRQ_PIT1 instead of MCFINT_VECBASE + MCFINT_PIT1 so we can support those parts that have the pit1 interrupt on other than the first interrupt controller. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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@ -62,6 +62,7 @@
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#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
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#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
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#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
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/*
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* SDRAM configuration registers.
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@ -52,6 +52,7 @@
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#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
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#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
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#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
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/*
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* SDRAM configuration registers.
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@ -60,6 +60,7 @@
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#define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1)
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#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
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#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
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/*
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* SDRAM configuration registers.
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@ -52,7 +52,7 @@
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#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
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#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
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#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
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/*
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* SDRAM configuration registers.
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*/
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@ -93,7 +93,7 @@ struct clock_event_device cf_pit_clockevent = {
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.set_mode = init_cf_pit_timer,
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.set_next_event = cf_pit_next_event,
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.shift = 32,
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.irq = MCFINT_VECBASE + MCFINT_PIT1,
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.irq = MCF_IRQ_PIT1,
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};
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@ -159,7 +159,7 @@ void hw_timer_init(irq_handler_t handler)
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clockevent_delta2ns(0x3f, &cf_pit_clockevent);
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clockevents_register_device(&cf_pit_clockevent);
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setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq);
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setup_irq(MCF_IRQ_PIT1, &pit_irq);
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clocksource_register_hz(&pit_clk, FREQ);
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}
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