ARM: entry: abort-macro: specify registers to be used for macros
Require all callers of abort macros to specify the registers to be used. This improves the documentation at the callsites as to which registers are being used by this assembly code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -22,7 +22,7 @@
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ENTRY(v4t_early_abort)
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ENTRY(v4t_early_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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do_thumb_abort
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do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
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ldreq r3, [r2] @ read aborted ARM instruction
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ldreq r3, [r2] @ read aborted ARM instruction
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bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
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bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
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tst r3, #1 << 20 @ check write
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tst r3, #1 << 20 @ check write
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@ -22,10 +22,10 @@
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ENTRY(v5t_early_abort)
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ENTRY(v5t_early_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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do_thumb_abort
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do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
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ldreq r3, [r2] @ read aborted ARM instruction
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ldreq r3, [r2] @ read aborted ARM instruction
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bic r1, r1, #1 << 11 @ clear bits 11 of FSR
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bic r1, r1, #1 << 11 @ clear bits 11 of FSR
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do_ldrd_abort
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do_ldrd_abort tmp=r2, insn=r3
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tst r3, #1 << 20 @ check write
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tst r3, #1 << 20 @ check write
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orreq r1, r1, #1 << 11
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orreq r1, r1, #1 << 11
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mov pc, lr
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mov pc, lr
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@ -25,9 +25,9 @@ ENTRY(v5tj_early_abort)
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bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
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bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
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tst r3, #PSR_J_BIT @ Java?
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tst r3, #PSR_J_BIT @ Java?
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movne pc, lr
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movne pc, lr
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do_thumb_abort
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do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
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ldreq r3, [r2] @ read aborted ARM instruction
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ldreq r3, [r2] @ read aborted ARM instruction
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do_ldrd_abort
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do_ldrd_abort tmp=r2, insn=r3
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tst r3, #1 << 20 @ L = 0 -> write
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tst r3, #1 << 20 @ L = 0 -> write
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orreq r1, r1, #1 << 11 @ yes.
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orreq r1, r1, #1 << 11 @ yes.
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mov pc, lr
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mov pc, lr
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@ -35,12 +35,12 @@ ENTRY(v6_early_abort)
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bic r1, r1, #1 << 11 @ clear bit 11 of FSR
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bic r1, r1, #1 << 11 @ clear bit 11 of FSR
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tst r3, #PSR_J_BIT @ Java?
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tst r3, #PSR_J_BIT @ Java?
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movne pc, lr
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movne pc, lr
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do_thumb_abort
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do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
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ldreq r3, [r2] @ read aborted ARM instruction
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ldreq r3, [r2] @ read aborted ARM instruction
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#ifdef CONFIG_CPU_ENDIAN_BE8
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#ifdef CONFIG_CPU_ENDIAN_BE8
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reveq r3, r3
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reveq r3, r3
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#endif
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#endif
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do_ldrd_abort
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do_ldrd_abort tmp=r2, insn=r3
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tst r3, #1 << 20 @ L = 0 -> write
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tst r3, #1 << 20 @ L = 0 -> write
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orreq r1, r1, #1 << 11 @ yes.
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orreq r1, r1, #1 << 11 @ yes.
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mov pc, lr
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mov pc, lr
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@ -9,33 +9,33 @@
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*
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*
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*/
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*/
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.macro do_thumb_abort
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.macro do_thumb_abort, fsr, pc, psr, tmp
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tst r3, #PSR_T_BIT
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tst \psr, #PSR_T_BIT
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beq not_thumb
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beq not_thumb
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ldrh r3, [r2] @ Read aborted Thumb instruction
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ldrh \tmp, [\pc] @ Read aborted Thumb instruction
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and r3, r3, # 0xfe00 @ Mask opcode field
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and \tmp, \tmp, # 0xfe00 @ Mask opcode field
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cmp r3, # 0x5600 @ Is it ldrsb?
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cmp \tmp, # 0x5600 @ Is it ldrsb?
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orreq r3, r3, #1 << 11 @ Set L-bit if yes
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orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes
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tst r3, #1 << 11 @ L = 0 -> write
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tst \tmp, #1 << 11 @ L = 0 -> write
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orreq r1, r1, #1 << 11 @ yes.
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orreq \psr, \psr, #1 << 11 @ yes.
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mov pc, lr
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mov pc, lr
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not_thumb:
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not_thumb:
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.endm
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.endm
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/*
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/*
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* We check for the following insturction encoding for LDRD.
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* We check for the following instruction encoding for LDRD.
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*
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*
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* [27:25] == 0
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* [27:25] == 000
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* [7:4] == 1101
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* [7:4] == 1101
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* [20] == 0
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* [20] == 0
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*/
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*/
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.macro do_ldrd_abort
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.macro do_ldrd_abort, tmp, insn
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tst r3, #0x0e000000 @ [27:25] == 0
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tst \insn, #0x0e000000 @ [27:25] == 0
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bne not_ldrd
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bne not_ldrd
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and r2, r3, #0x000000f0 @ [7:4] == 1101
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and \tmp, \insn, #0x000000f0 @ [7:4] == 1101
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cmp r2, #0x000000d0
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cmp \tmp, #0x000000d0
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bne not_ldrd
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bne not_ldrd
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tst r3, #1 << 20 @ [20] == 0
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tst \insn, #1 << 20 @ [20] == 0
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moveq pc, lr
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moveq pc, lr
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not_ldrd:
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not_ldrd:
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.endm
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.endm
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