drm/mediatek: separate hdmi phy to different file
Different IC has different phy setting of HDMI. This patch separates the phy hardware relate part for mt8173. Signed-off-by: chunhui dai <chunhui.dai@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>hifive-unleashed-5.1
chunhui dai
CK Hu
parent
d08b5ab972
commit
be28b6507c
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@ -1,4 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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mediatek-drm-y := mtk_disp_color.o \
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mtk_disp_ovl.o \
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mtk_disp_rdma.o \
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@ -18,6 +19,7 @@ obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
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mediatek-drm-hdmi-objs := mtk_cec.o \
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mtk_hdmi.o \
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mtk_hdmi_ddc.o \
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mtk_mt8173_hdmi_phy.o
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mtk_mt8173_hdmi_phy.o \
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mtk_hdmi_phy.o
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obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
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obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
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@ -233,6 +233,7 @@ static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
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static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
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{
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struct arm_smccc_res res;
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struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy);
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/*
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* MT8173 HDMI hardware has an output control bit to enable/disable HDMI
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@ -13,11 +13,11 @@
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*/
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#ifndef _MTK_HDMI_CTRL_H
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#define _MTK_HDMI_CTRL_H
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#include "mtk_hdmi_phy.h"
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struct platform_driver;
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extern struct platform_driver mtk_cec_driver;
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extern struct platform_driver mtk_hdmi_ddc_driver;
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extern struct platform_driver mtk_hdmi_phy_driver;
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#endif /* _MTK_HDMI_CTRL_H */
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@ -0,0 +1,232 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Jie Qiu <jie.qiu@mediatek.com>
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*/
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#include "mtk_hdmi_phy.h"
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static int mtk_hdmi_phy_power_on(struct phy *phy);
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static int mtk_hdmi_phy_power_off(struct phy *phy);
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static const struct phy_ops mtk_hdmi_phy_dev_ops = {
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.power_on = mtk_hdmi_phy_power_on,
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.power_off = mtk_hdmi_phy_power_off,
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.owner = THIS_MODULE,
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};
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long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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hdmi_phy->pll_rate = rate;
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if (rate <= 74250000)
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*parent_rate = rate;
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else
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*parent_rate = rate / 2;
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return rate;
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}
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unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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return hdmi_phy->pll_rate;
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}
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void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
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u32 bits)
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{
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void __iomem *reg = hdmi_phy->regs + offset;
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u32 tmp;
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tmp = readl(reg);
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tmp &= ~bits;
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writel(tmp, reg);
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}
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void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
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u32 bits)
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{
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void __iomem *reg = hdmi_phy->regs + offset;
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u32 tmp;
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tmp = readl(reg);
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tmp |= bits;
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writel(tmp, reg);
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}
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void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
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u32 val, u32 mask)
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{
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void __iomem *reg = hdmi_phy->regs + offset;
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u32 tmp;
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tmp = readl(reg);
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tmp = (tmp & ~mask) | (val & mask);
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writel(tmp, reg);
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}
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inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
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{
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return container_of(hw, struct mtk_hdmi_phy, pll_hw);
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}
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static int mtk_hdmi_phy_power_on(struct phy *phy)
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{
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struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
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int ret;
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ret = clk_prepare_enable(hdmi_phy->pll);
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if (ret < 0)
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return ret;
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hdmi_phy->conf->hdmi_phy_enable_tmds(hdmi_phy);
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return 0;
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}
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static int mtk_hdmi_phy_power_off(struct phy *phy)
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{
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struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
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hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
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clk_disable_unprepare(hdmi_phy->pll);
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return 0;
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}
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static const struct phy_ops *
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mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
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{
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if (hdmi_phy && hdmi_phy->conf &&
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hdmi_phy->conf->hdmi_phy_enable_tmds &&
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hdmi_phy->conf->hdmi_phy_disable_tmds)
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return &mtk_hdmi_phy_dev_ops;
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dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
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return NULL;
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}
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static void mtk_hdmi_phy_clk_get_ops(struct mtk_hdmi_phy *hdmi_phy,
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const struct clk_ops **ops)
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{
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if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_clk_ops)
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*ops = hdmi_phy->conf->hdmi_phy_clk_ops;
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else
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dev_err(hdmi_phy->dev, "Failed to get clk ops of phy\n");
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}
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static int mtk_hdmi_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mtk_hdmi_phy *hdmi_phy;
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struct resource *mem;
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struct clk *ref_clk;
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const char *ref_clk_name;
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struct clk_init_data clk_init = {
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.num_parents = 1,
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.parent_names = (const char * const *)&ref_clk_name,
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.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
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};
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struct phy *phy;
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struct phy_provider *phy_provider;
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int ret;
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hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
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if (!hdmi_phy)
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return -ENOMEM;
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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hdmi_phy->regs = devm_ioremap_resource(dev, mem);
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if (IS_ERR(hdmi_phy->regs)) {
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ret = PTR_ERR(hdmi_phy->regs);
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dev_err(dev, "Failed to get memory resource: %d\n", ret);
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return ret;
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}
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ref_clk = devm_clk_get(dev, "pll_ref");
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if (IS_ERR(ref_clk)) {
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ret = PTR_ERR(ref_clk);
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dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
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ret);
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return ret;
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}
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ref_clk_name = __clk_get_name(ref_clk);
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ret = of_property_read_string(dev->of_node, "clock-output-names",
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&clk_init.name);
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if (ret < 0) {
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dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
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return ret;
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}
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hdmi_phy->dev = dev;
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hdmi_phy->conf =
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(struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
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mtk_hdmi_phy_clk_get_ops(hdmi_phy, &clk_init.ops);
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hdmi_phy->pll_hw.init = &clk_init;
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hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
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if (IS_ERR(hdmi_phy->pll)) {
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ret = PTR_ERR(hdmi_phy->pll);
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dev_err(dev, "Failed to register PLL: %d\n", ret);
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return ret;
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}
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ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
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&hdmi_phy->ibias);
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if (ret < 0) {
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dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
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return ret;
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}
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ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
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&hdmi_phy->ibias_up);
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if (ret < 0) {
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dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
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return ret;
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}
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dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
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hdmi_phy->drv_imp_clk = 0x30;
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hdmi_phy->drv_imp_d2 = 0x30;
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hdmi_phy->drv_imp_d1 = 0x30;
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hdmi_phy->drv_imp_d0 = 0x30;
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phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
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if (IS_ERR(phy)) {
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dev_err(dev, "Failed to create HDMI PHY\n");
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return PTR_ERR(phy);
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}
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phy_set_drvdata(phy, hdmi_phy);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (IS_ERR(phy_provider)) {
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dev_err(dev, "Failed to register HDMI PHY\n");
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return PTR_ERR(phy_provider);
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}
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return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
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hdmi_phy->pll);
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}
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static const struct of_device_id mtk_hdmi_phy_match[] = {
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{ .compatible = "mediatek,mt8173-hdmi-phy",
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.data = &mtk_hdmi_phy_8173_conf,
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},
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{},
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};
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struct platform_driver mtk_hdmi_phy_driver = {
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.probe = mtk_hdmi_phy_probe,
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.driver = {
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.name = "mediatek-hdmi-phy",
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.of_match_table = mtk_hdmi_phy_match,
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},
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};
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MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
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MODULE_LICENSE("GPL v2");
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@ -0,0 +1,58 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Chunhui Dai <chunhui.dai@mediatek.com>
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*/
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#ifndef _MTK_HDMI_PHY_H
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#define _MTK_HDMI_PHY_H
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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struct mtk_hdmi_phy;
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struct mtk_hdmi_phy_conf {
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const struct clk_ops *hdmi_phy_clk_ops;
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void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
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void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
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};
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struct mtk_hdmi_phy {
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void __iomem *regs;
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struct device *dev;
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struct mtk_hdmi_phy_conf *conf;
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struct clk *pll;
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struct clk_hw pll_hw;
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unsigned long pll_rate;
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unsigned char drv_imp_clk;
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unsigned char drv_imp_d2;
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unsigned char drv_imp_d1;
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unsigned char drv_imp_d0;
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unsigned int ibias;
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unsigned int ibias_up;
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};
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void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
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u32 bits);
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void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
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u32 bits);
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void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
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u32 val, u32 mask);
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struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
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long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate);
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unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate);
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extern struct platform_driver mtk_hdmi_phy_driver;
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extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
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#endif /* _MTK_HDMI_PHY_H */
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@ -12,15 +12,7 @@
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include "mtk_hdmi_phy.h"
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#define HDMI_CON0 0x00
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#define RG_HDMITX_PLL_EN BIT(31)
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@ -123,20 +115,6 @@
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#define RGS_HDMITX_5T1_EDG (0xf << 4)
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#define RGS_HDMITX_PLUG_TST BIT(0)
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struct mtk_hdmi_phy {
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void __iomem *regs;
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struct device *dev;
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struct clk *pll;
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struct clk_hw pll_hw;
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unsigned long pll_rate;
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u8 drv_imp_clk;
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u8 drv_imp_d2;
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u8 drv_imp_d1;
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u8 drv_imp_d0;
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u32 ibias;
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u32 ibias_up;
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};
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static const u8 PREDIV[3][4] = {
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{0x0, 0x0, 0x0, 0x0}, /* 27Mhz */
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{0x1, 0x1, 0x1, 0x1}, /* 74Mhz */
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@ -185,44 +163,6 @@ static const u8 HTPLLBR[3][4] = {
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{0x1, 0x2, 0x2, 0x1} /* 148Mhz */
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};
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static void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
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u32 bits)
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{
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void __iomem *reg = hdmi_phy->regs + offset;
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u32 tmp;
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tmp = readl(reg);
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tmp &= ~bits;
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writel(tmp, reg);
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}
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static void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
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u32 bits)
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{
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void __iomem *reg = hdmi_phy->regs + offset;
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u32 tmp;
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tmp = readl(reg);
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tmp |= bits;
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writel(tmp, reg);
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}
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static void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
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u32 val, u32 mask)
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{
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void __iomem *reg = hdmi_phy->regs + offset;
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u32 tmp;
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tmp = readl(reg);
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tmp = (tmp & ~mask) | (val & mask);
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writel(tmp, reg);
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}
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static inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
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{
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return container_of(hw, struct mtk_hdmi_phy, pll_hw);
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}
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static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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@ -345,29 +285,7 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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return 0;
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}
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static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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hdmi_phy->pll_rate = rate;
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if (rate <= 74250000)
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*parent_rate = rate;
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else
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*parent_rate = rate / 2;
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return rate;
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}
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static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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return hdmi_phy->pll_rate;
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||||
}
|
||||
|
||||
static const struct clk_ops mtk_hdmi_pll_ops = {
|
||||
static const struct clk_ops mtk_hdmi_phy_pll_ops = {
|
||||
.prepare = mtk_hdmi_pll_prepare,
|
||||
.unprepare = mtk_hdmi_pll_unprepare,
|
||||
.set_rate = mtk_hdmi_pll_set_rate,
|
||||
|
|
@ -390,142 +308,10 @@ static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
|
|||
RG_HDMITX_SER_EN);
|
||||
}
|
||||
|
||||
static int mtk_hdmi_phy_power_on(struct phy *phy)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(hdmi_phy->pll);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
mtk_hdmi_phy_enable_tmds(hdmi_phy);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_hdmi_phy_power_off(struct phy *phy)
|
||||
{
|
||||
struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
|
||||
|
||||
mtk_hdmi_phy_disable_tmds(hdmi_phy);
|
||||
clk_disable_unprepare(hdmi_phy->pll);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct phy_ops mtk_hdmi_phy_ops = {
|
||||
.power_on = mtk_hdmi_phy_power_on,
|
||||
.power_off = mtk_hdmi_phy_power_off,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static int mtk_hdmi_phy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct mtk_hdmi_phy *hdmi_phy;
|
||||
struct resource *mem;
|
||||
struct clk *ref_clk;
|
||||
const char *ref_clk_name;
|
||||
struct clk_init_data clk_init = {
|
||||
.ops = &mtk_hdmi_pll_ops,
|
||||
.num_parents = 1,
|
||||
.parent_names = (const char * const *)&ref_clk_name,
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
|
||||
};
|
||||
struct phy *phy;
|
||||
struct phy_provider *phy_provider;
|
||||
int ret;
|
||||
|
||||
hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
|
||||
if (!hdmi_phy)
|
||||
return -ENOMEM;
|
||||
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
hdmi_phy->regs = devm_ioremap_resource(dev, mem);
|
||||
if (IS_ERR(hdmi_phy->regs)) {
|
||||
ret = PTR_ERR(hdmi_phy->regs);
|
||||
dev_err(dev, "Failed to get memory resource: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ref_clk = devm_clk_get(dev, "pll_ref");
|
||||
if (IS_ERR(ref_clk)) {
|
||||
ret = PTR_ERR(ref_clk);
|
||||
dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
ref_clk_name = __clk_get_name(ref_clk);
|
||||
|
||||
ret = of_property_read_string(dev->of_node, "clock-output-names",
|
||||
&clk_init.name);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
hdmi_phy->pll_hw.init = &clk_init;
|
||||
hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
|
||||
if (IS_ERR(hdmi_phy->pll)) {
|
||||
ret = PTR_ERR(hdmi_phy->pll);
|
||||
dev_err(dev, "Failed to register PLL: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
|
||||
&hdmi_phy->ibias);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
|
||||
&hdmi_phy->ibias_up);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
|
||||
hdmi_phy->drv_imp_clk = 0x30;
|
||||
hdmi_phy->drv_imp_d2 = 0x30;
|
||||
hdmi_phy->drv_imp_d1 = 0x30;
|
||||
hdmi_phy->drv_imp_d0 = 0x30;
|
||||
|
||||
phy = devm_phy_create(dev, NULL, &mtk_hdmi_phy_ops);
|
||||
if (IS_ERR(phy)) {
|
||||
dev_err(dev, "Failed to create HDMI PHY\n");
|
||||
return PTR_ERR(phy);
|
||||
}
|
||||
phy_set_drvdata(phy, hdmi_phy);
|
||||
|
||||
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
if (IS_ERR(phy_provider))
|
||||
return PTR_ERR(phy_provider);
|
||||
|
||||
hdmi_phy->dev = dev;
|
||||
return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
|
||||
hdmi_phy->pll);
|
||||
}
|
||||
|
||||
static int mtk_hdmi_phy_remove(struct platform_device *pdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id mtk_hdmi_phy_match[] = {
|
||||
{ .compatible = "mediatek,mt8173-hdmi-phy", },
|
||||
{},
|
||||
};
|
||||
|
||||
struct platform_driver mtk_hdmi_phy_driver = {
|
||||
.probe = mtk_hdmi_phy_probe,
|
||||
.remove = mtk_hdmi_phy_remove,
|
||||
.driver = {
|
||||
.name = "mediatek-hdmi-phy",
|
||||
.of_match_table = mtk_hdmi_phy_match,
|
||||
},
|
||||
struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
|
||||
.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
|
||||
.hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds,
|
||||
.hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
|
||||
};
|
||||
|
||||
MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
|
||||
|
|
|
|||
Loading…
Reference in New Issue