arm64: capabilities: Add support for checks based on a list of MIDRs
Add helpers for detecting an errata on list of midr ranges of affected CPUs, with the same work around. Cc: Will Deacon <will.deacon@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Dave Martin <dave.martin@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -314,6 +314,7 @@ struct arm64_cpu_capabilities {
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} * const fixed_revs;
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};
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const struct midr_range *midr_range_list;
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struct { /* Feature register checking */
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u32 sys_reg;
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u8 field_pos;
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@ -147,6 +147,15 @@ static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)
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range->rv_min, range->rv_max);
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}
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static inline bool
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is_midr_in_range_list(u32 midr, struct midr_range const *ranges)
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{
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while (ranges->model)
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if (is_midr_in_range(midr, ranges++))
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return true;
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return false;
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}
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/*
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* The CPU ID never changes at run time, so we might as well tell the
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* compiler that it's constant. Use this function to read the CPU ID
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@ -40,6 +40,14 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
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return true;
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}
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static bool __maybe_unused
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is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
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}
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static bool __maybe_unused
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is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
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{
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@ -250,6 +258,10 @@ qcom_enable_link_stack_sanitization(const struct arm64_cpu_capabilities *entry)
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
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#define CAP_MIDR_RANGE_LIST(list) \
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.matches = is_affected_midr_range_list, \
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.midr_range_list = list
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/* Errata affecting a range of revisions of given model variant */
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#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
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ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
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@ -263,6 +275,35 @@ qcom_enable_link_stack_sanitization(const struct arm64_cpu_capabilities *entry)
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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CAP_MIDR_ALL_VERSIONS(model)
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/* Errata affecting a list of midr ranges, with same work around */
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#define ERRATA_MIDR_RANGE_LIST(midr_list) \
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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CAP_MIDR_RANGE_LIST(midr_list)
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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/*
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* List of CPUs where we need to issue a psci call to
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* harden the branch predictor.
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*/
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static const struct midr_range arm64_bp_harden_smccc_cpus[] = {
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
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MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
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MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
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{},
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};
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static const struct midr_range qcom_bp_harden_cpus[] = {
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
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{},
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};
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#endif
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const struct arm64_cpu_capabilities arm64_errata[] = {
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#if defined(CONFIG_ARM64_ERRATUM_826319) || \
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defined(CONFIG_ARM64_ERRATUM_827319) || \
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@ -406,51 +447,17 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
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ERRATA_MIDR_RANGE_LIST(arm64_bp_harden_smccc_cpus),
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.cpu_enable = enable_smccc_arch_workaround_1,
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
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.cpu_enable = enable_smccc_arch_workaround_1,
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
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.cpu_enable = enable_smccc_arch_workaround_1,
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
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.cpu_enable = enable_smccc_arch_workaround_1,
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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ERRATA_MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
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ERRATA_MIDR_RANGE_LIST(qcom_bp_harden_cpus),
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.cpu_enable = qcom_enable_link_stack_sanitization,
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},
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{
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.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
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ERRATA_MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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ERRATA_MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
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.cpu_enable = qcom_enable_link_stack_sanitization,
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},
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{
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.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
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ERRATA_MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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ERRATA_MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
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.cpu_enable = enable_smccc_arch_workaround_1,
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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ERRATA_MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
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.cpu_enable = enable_smccc_arch_workaround_1,
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ERRATA_MIDR_RANGE_LIST(qcom_bp_harden_cpus),
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},
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#endif
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{
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@ -882,6 +882,11 @@ static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
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static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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/* List of CPUs that are not vulnerable and don't need KPTI */
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static const struct midr_range kpti_safe_list[] = {
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MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
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MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
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};
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char const *str = "command line option";
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/*
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@ -906,11 +911,8 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
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return true;
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/* Don't force KPTI for CPUs that are not vulnerable */
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switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) {
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case MIDR_CAVIUM_THUNDERX2:
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case MIDR_BRCM_VULCAN:
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if (is_midr_in_range_list(read_cpuid_id(), kpti_safe_list))
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return false;
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}
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/* Defer to CPU feature registers */
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return !has_cpuid_feature(entry, scope);
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