KVM: MIPS/T&E: Default to reset vector
Set the default VCPU state closer to the architectural reset state, with PC pointing at the reset vector (uncached PA 0x1fc00000, which for KVM T&E is VA 0x5fc00000), and with CP0_Status.BEV and CP0_Status.ERL to 1. Although QEMU at least will overwrite this state, it makes sense to do this now that CP0_EBase is properly implemented to check BEV, and now that we support a sparse GPA layout potentially with a boot ROM at GPA 0x1fc00000. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org
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@ -614,6 +614,9 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
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/* Set Wait IE/IXMT Ignore in Config7, IAR, AR */
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kvm_write_c0_guest_config7(cop0, (MIPS_CONF7_WII) | (1 << 10));
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/* Status */
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kvm_write_c0_guest_status(cop0, ST0_BEV | ST0_ERL);
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/*
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* Setup IntCtl defaults, compatibility mode for timer interrupts (HW5)
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*/
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@ -623,6 +626,9 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
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kvm_write_c0_guest_ebase(cop0, KVM_GUEST_KSEG0 |
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(vcpu_id & MIPS_EBASE_CPUNUM));
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/* Put PC at guest reset vector */
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vcpu->arch.pc = KVM_GUEST_CKSEG1ADDR(0x1fc00000);
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return 0;
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}
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