mlxsw: pci: Fix size of trap_id field in CQE
The "trap_id" is 9bits long. So far, this was not a problem since we
used only traps with ids that fit into 8bits. But the ACL traps that are
going to be introduced use the 9th bit.
Fixes: eda6500a98
("mlxsw: Add PCI bus implementation")
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Reviewed-by: Yotam Gigi <yotamg@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -155,7 +155,7 @@ MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
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/* pci_cqe_trap_id
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* Trap ID that captured the packet.
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*/
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MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 8);
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MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 9);
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/* pci_cqe_crc
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* Length include CRC. Indicates the length field includes
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