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qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC 

Add initial dts files and SoC support for IPQ4019

Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
hifive-unleashed-5.1
Matthew McClintock 2015-11-19 17:19:31 -06:00 committed by Andy Gross
parent f55532a0c0
commit bec6ba4cdf
1 changed files with 115 additions and 0 deletions
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115
arch/arm/boot/dts/qcom-ipq4019.dtsi 100644
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/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "skeleton.dtsi"
#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
/ {
model = "Qualcomm Technologies, Inc. IPQ4019";
compatible = "qcom,ipq4019";
interrupt-parent = <&intc>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
};
};
clocks {
sleep_clk: sleep_clk {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x0b000000 0x1000>,
<0x0b002000 0x1000>;
};
gcc: clock-controller@1800000 {
compatible = "qcom,gcc-ipq4019";
#clock-cells = <1>;
#reset-cells = <1>;
reg = <0x1800000 0x60000>;
};
tlmm: pinctrl@0x01000000 {
compatible = "qcom,ipq4019-pinctrl";
reg = <0x01000000 0x300000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 208 0>;
};
serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
interrupts = <0 107 0>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
};
serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b0000 0x200>;
interrupts = <0 108 0>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
};
};
};