Merge tag 'drm-intel-fixes-2015-08-20' of git://anongit.freedesktop.org/drm-intel into drm-fixes
Revert of a VBT parsing commit that should've been queued for drm-next, not v4.2. The revert unbreaks Braswell among other things. Also on Braswell removal of DP HBR2/TP3 and intermediate eDP frequency support. The code was optimistically added based on incorrect documentation; the platform does not support them. These are cc: stable. Finally a gpu state fix from Chris, also cc: stable. * tag 'drm-intel-fixes-2015-08-20' of git://anongit.freedesktop.org/drm-intel: drm/i915: Avoid TP3 on CHV drm/i915: remove HBR2 from chv supported list Revert "drm/i915: Add eDP intermediate frequencies for CHV" Revert "drm/i915: Allow parsing of variable size child device entries from VBT" drm/i915: Flag the execlists context object as dirty after every use
This commit is contained in:
commit
bef7d1961c
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@ -1075,7 +1075,6 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
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const union child_device_config *p_child;
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union child_device_config *child_dev_ptr;
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int i, child_device_num, count;
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u8 expected_size;
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u16 block_size;
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p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
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@ -1083,26 +1082,8 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
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DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n");
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return;
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}
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if (bdb->version < 195) {
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expected_size = 33;
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} else if (bdb->version == 195) {
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expected_size = 37;
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} else if (bdb->version <= 197) {
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expected_size = 38;
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} else {
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expected_size = 38;
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DRM_DEBUG_DRIVER("Expected child_device_config size for BDB version %u not known; assuming %u\n",
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expected_size, bdb->version);
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}
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if (expected_size > sizeof(*p_child)) {
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DRM_ERROR("child_device_config cannot fit in p_child\n");
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return;
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}
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if (p_defs->child_dev_size != expected_size) {
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DRM_ERROR("Size mismatch; child_device_config size=%u (expected %u); bdb->version: %u\n",
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p_defs->child_dev_size, expected_size, bdb->version);
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if (p_defs->child_dev_size < sizeof(*p_child)) {
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DRM_ERROR("General definiton block child device size is too small.\n");
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return;
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}
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/* get the block size of general definitions */
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@ -1149,7 +1130,7 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
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child_dev_ptr = dev_priv->vbt.child_dev + count;
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count++;
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memcpy(child_dev_ptr, p_child, p_defs->child_dev_size);
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memcpy(child_dev_ptr, p_child, sizeof(*p_child));
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}
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return;
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}
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@ -93,9 +93,6 @@ static const struct dp_link_dpll chv_dpll[] = {
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static const int skl_rates[] = { 162000, 216000, 270000,
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324000, 432000, 540000 };
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static const int chv_rates[] = { 162000, 202500, 210000, 216000,
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243000, 270000, 324000, 405000,
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420000, 432000, 540000 };
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static const int default_rates[] = { 162000, 270000, 540000 };
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/**
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@ -1169,24 +1166,31 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
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return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
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}
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static bool intel_dp_source_supports_hbr2(struct drm_device *dev)
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{
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/* WaDisableHBR2:skl */
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if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
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return false;
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if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
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(INTEL_INFO(dev)->gen >= 9))
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return true;
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else
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return false;
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}
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static int
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intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
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{
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if (IS_SKYLAKE(dev)) {
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*source_rates = skl_rates;
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return ARRAY_SIZE(skl_rates);
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} else if (IS_CHERRYVIEW(dev)) {
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*source_rates = chv_rates;
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return ARRAY_SIZE(chv_rates);
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}
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*source_rates = default_rates;
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if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
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/* WaDisableHBR2:skl */
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return (DP_LINK_BW_2_7 >> 3) + 1;
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else if (INTEL_INFO(dev)->gen >= 8 ||
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(IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
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/* This depends on the fact that 5.4 is last value in the array */
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if (intel_dp_source_supports_hbr2(dev))
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return (DP_LINK_BW_5_4 >> 3) + 1;
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else
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return (DP_LINK_BW_2_7 >> 3) + 1;
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@ -3941,10 +3945,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
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}
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}
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/* Training Pattern 3 support, both source and sink */
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/* Training Pattern 3 support, Intel platforms that support HBR2 alone
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* have support for TP3 hence that check is used along with dpcd check
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* to ensure TP3 can be enabled.
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* SKL < B0: due it's WaDisableHBR2 is the only exception where TP3 is
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* supported but still not enabled.
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*/
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if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
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intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
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(IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
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intel_dp_source_supports_hbr2(dev)) {
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intel_dp->use_tps3 = true;
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DRM_DEBUG_KMS("Displayport TPS3 supported\n");
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} else
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@ -1012,6 +1012,8 @@ static int intel_lr_context_pin(struct intel_engine_cs *ring,
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ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
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if (ret)
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goto unpin_ctx_obj;
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ctx_obj->dirty = true;
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}
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return ret;
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