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MLK-23372 perf/imx_ddr: correct CLEAR bit definition 

ddr_perf_event_stop will firstly call ddr_perf_counter_enable to disable
the counter, and then call ddr_perf_event_update to read the counter value.

When disable the counter, it will write 0 into COUNTER_CNTL[CLEAR] bit
which cause the counter value cleared. Counter value will always be 0
when update the counter.

The correct definition of CLEAR bit is that write 0 to clear the counter
value.

Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Joakim Zhang 2020-02-24 13:08:05 +08:00
parent d056a46170
commit befb57153a
1 changed files with 6 additions and 4 deletions
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10
drivers/perf/fsl_imx8_ddr_perf.c
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@ -396,9 +396,10 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
if (enable) {
/*
* must disable first, then enable again
* otherwise, cycle counter will not work
* if previous state is enabled.
* cycle counter is special which should firstly write 0 then
* write 1 into CLEAR bit to clear it. Other counters only
* need write 0 into CLEAR bit and it turns out to be 1 by
* hardware. Below enable flow is harmless for all counters.
*/
writel(0, pmu->base + reg);
val = CNTL_EN | CNTL_CLEAR;
@ -420,7 +421,8 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
writel(val, pmu->base + reg);
} else {
/* Disable counter */
writel(0, pmu->base + reg);
val = readl(pmu->base + reg) & CNTL_EN_MASK;
writel(val, pmu->base + reg);
}
}