drm/i915: add support for per-pipe power sequencing on vlv
VLV has per-pipe PP registers. Set up power sequencing on mode set. The connector init time setup is problematic, since we don't have a pipe at that time. Cook up something. v2: - use vlv_power_sequencer_pipe() also in _pp_{ctrl,stat}_reg() - use PANEL_PORT_SELECT_DPC_VLV (Ville) v3: make checkpatch happier Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [danvet: Make checkpatch a bit more happier still ...] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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a24c144cc9
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@ -237,24 +237,77 @@ intel_hrawclk(struct drm_device *dev)
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}
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}
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static void
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intel_dp_init_panel_power_sequencer(struct drm_device *dev,
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struct intel_dp *intel_dp,
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struct edp_power_seq *out);
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static void
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intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
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struct intel_dp *intel_dp,
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struct edp_power_seq *out);
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static enum pipe
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vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
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struct drm_device *dev = intel_dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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enum port port = intel_dig_port->port;
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enum pipe pipe;
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/* modeset should have pipe */
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if (crtc)
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return to_intel_crtc(crtc)->pipe;
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/* init time, try to find a pipe with this port selected */
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for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
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u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
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PANEL_PORT_SELECT_MASK;
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if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
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return pipe;
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if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
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return pipe;
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}
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/* shrug */
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return PIPE_A;
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}
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static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
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{
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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if (HAS_PCH_SPLIT(dev))
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return PCH_PP_CONTROL;
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else
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return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
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}
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static u32 _pp_stat_reg(struct intel_dp *intel_dp)
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{
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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if (HAS_PCH_SPLIT(dev))
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return PCH_PP_STATUS;
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else
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return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
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}
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static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
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{
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pp_stat_reg;
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pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
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return (I915_READ(pp_stat_reg) & PP_ON) != 0;
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return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
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}
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static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
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{
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pp_ctrl_reg;
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
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return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
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}
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static void
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@ -262,19 +315,15 @@ intel_dp_check_edp(struct intel_dp *intel_dp)
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{
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pp_stat_reg, pp_ctrl_reg;
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if (!is_edp(intel_dp))
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return;
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pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
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WARN(1, "eDP powered off while attempting aux channel communication.\n");
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DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
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I915_READ(pp_stat_reg),
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I915_READ(pp_ctrl_reg));
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I915_READ(_pp_stat_reg(intel_dp)),
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I915_READ(_pp_ctrl_reg(intel_dp)));
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}
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}
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@ -948,8 +997,8 @@ static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pp_stat_reg, pp_ctrl_reg;
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pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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pp_stat_reg = _pp_stat_reg(intel_dp);
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pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
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DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
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mask, value,
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@ -991,11 +1040,8 @@ static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 control;
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u32 pp_ctrl_reg;
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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control = I915_READ(pp_ctrl_reg);
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control = I915_READ(_pp_ctrl_reg(intel_dp));
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control &= ~PANEL_UNLOCK_MASK;
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control |= PANEL_UNLOCK_REGS;
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return control;
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@ -1028,8 +1074,8 @@ void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
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pp = ironlake_get_pp_control(intel_dp);
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pp |= EDP_FORCE_VDD;
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pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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pp_stat_reg = _pp_stat_reg(intel_dp);
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pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
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I915_WRITE(pp_ctrl_reg, pp);
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POSTING_READ(pp_ctrl_reg);
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@ -1057,8 +1103,8 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
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pp = ironlake_get_pp_control(intel_dp);
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pp &= ~EDP_FORCE_VDD;
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pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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pp_stat_reg = _pp_ctrl_reg(intel_dp);
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pp_ctrl_reg = _pp_stat_reg(intel_dp);
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I915_WRITE(pp_ctrl_reg, pp);
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POSTING_READ(pp_ctrl_reg);
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@ -1123,20 +1169,19 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
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ironlake_wait_panel_power_cycle(intel_dp);
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pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
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pp = ironlake_get_pp_control(intel_dp);
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if (IS_GEN5(dev)) {
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/* ILK workaround: disable reset around power sequence */
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pp &= ~PANEL_POWER_RESET;
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I915_WRITE(PCH_PP_CONTROL, pp);
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POSTING_READ(PCH_PP_CONTROL);
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I915_WRITE(pp_ctrl_reg, pp);
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POSTING_READ(pp_ctrl_reg);
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}
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pp |= POWER_TARGET_ON;
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if (!IS_GEN5(dev))
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pp |= PANEL_POWER_RESET;
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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I915_WRITE(pp_ctrl_reg, pp);
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POSTING_READ(pp_ctrl_reg);
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@ -1144,8 +1189,8 @@ void ironlake_edp_panel_on(struct intel_dp *intel_dp)
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if (IS_GEN5(dev)) {
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pp |= PANEL_POWER_RESET; /* restore panel reset bit */
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I915_WRITE(PCH_PP_CONTROL, pp);
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POSTING_READ(PCH_PP_CONTROL);
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I915_WRITE(pp_ctrl_reg, pp);
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POSTING_READ(pp_ctrl_reg);
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}
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}
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@ -1168,7 +1213,7 @@ void ironlake_edp_panel_off(struct intel_dp *intel_dp)
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* panels get very unhappy and cease to work. */
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pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
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I915_WRITE(pp_ctrl_reg, pp);
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POSTING_READ(pp_ctrl_reg);
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@ -1201,7 +1246,7 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
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pp = ironlake_get_pp_control(intel_dp);
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pp |= EDP_BLC_ENABLE;
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
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I915_WRITE(pp_ctrl_reg, pp);
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POSTING_READ(pp_ctrl_reg);
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@ -1225,7 +1270,7 @@ void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
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pp = ironlake_get_pp_control(intel_dp);
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pp &= ~EDP_BLC_ENABLE;
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pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
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pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
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I915_WRITE(pp_ctrl_reg, pp);
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POSTING_READ(pp_ctrl_reg);
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@ -1752,6 +1797,7 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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int port = vlv_dport_to_channel(dport);
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int pipe = intel_crtc->pipe;
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struct edp_power_seq power_seq;
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u32 val;
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mutex_lock(&dev_priv->dpio_lock);
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@ -1769,6 +1815,11 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
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mutex_unlock(&dev_priv->dpio_lock);
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/* init power sequencer on this pipe and port */
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intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
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intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
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&power_seq);
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intel_enable_dp(encoder);
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vlv_wait_port_ready(dev_priv, port);
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@ -3161,24 +3212,26 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct edp_power_seq cur, vbt, spec, final;
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u32 pp_on, pp_off, pp_div, pp;
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int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
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int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
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if (HAS_PCH_SPLIT(dev)) {
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pp_control_reg = PCH_PP_CONTROL;
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pp_ctrl_reg = PCH_PP_CONTROL;
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pp_on_reg = PCH_PP_ON_DELAYS;
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pp_off_reg = PCH_PP_OFF_DELAYS;
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pp_div_reg = PCH_PP_DIVISOR;
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} else {
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pp_control_reg = PIPEA_PP_CONTROL;
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pp_on_reg = PIPEA_PP_ON_DELAYS;
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pp_off_reg = PIPEA_PP_OFF_DELAYS;
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pp_div_reg = PIPEA_PP_DIVISOR;
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enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
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pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
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pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
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pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
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pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
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}
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/* Workaround: Need to write PP_CONTROL with the unlock key as
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* the very first thing. */
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pp = ironlake_get_pp_control(intel_dp);
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I915_WRITE(pp_control_reg, pp);
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I915_WRITE(pp_ctrl_reg, pp);
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pp_on = I915_READ(pp_on_reg);
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pp_off = I915_READ(pp_off_reg);
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@ -3266,9 +3319,11 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
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pp_off_reg = PCH_PP_OFF_DELAYS;
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pp_div_reg = PCH_PP_DIVISOR;
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} else {
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pp_on_reg = PIPEA_PP_ON_DELAYS;
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pp_off_reg = PIPEA_PP_OFF_DELAYS;
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pp_div_reg = PIPEA_PP_DIVISOR;
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enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
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pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
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pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
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pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
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}
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/* And finally store the new values in the power sequencer. */
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@ -3285,7 +3340,10 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
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/* Haswell doesn't have any port selection bits for the panel
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* power sequencer any more. */
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if (IS_VALLEYVIEW(dev)) {
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port_sel = I915_READ(pp_on_reg) & 0xc0000000;
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if (dp_to_dig_port(intel_dp)->port == PORT_B)
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port_sel = PANEL_PORT_SELECT_DPB_VLV;
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else
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port_sel = PANEL_PORT_SELECT_DPC_VLV;
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} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
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if (dp_to_dig_port(intel_dp)->port == PORT_A)
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port_sel = PANEL_PORT_SELECT_DPA;
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