ath9k: Cleanup TX power calculation for 4K chips
Write CCK power-per-rate array always and report correct TX power to regulatory. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -703,11 +703,11 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
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}
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static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
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struct ath9k_channel *chan,
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u16 cfgCtl,
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u8 twiceAntennaReduction,
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u8 twiceMaxRegulatoryPower,
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u8 powerLimit)
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struct ath9k_channel *chan,
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u16 cfgCtl,
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u8 twiceAntennaReduction,
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u8 twiceMaxRegulatoryPower,
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u8 powerLimit)
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{
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struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
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struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
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@ -724,10 +724,10 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
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}
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ath9k_hw_set_4k_power_per_rate_table(ah, chan,
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&ratesArray[0], cfgCtl,
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twiceAntennaReduction,
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twiceMaxRegulatoryPower,
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powerLimit);
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&ratesArray[0], cfgCtl,
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twiceAntennaReduction,
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twiceMaxRegulatoryPower,
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powerLimit);
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ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
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@ -737,11 +737,23 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
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ratesArray[i] = AR5416_MAX_RATE_POWER;
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}
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/* Update regulatory */
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i = rate6mb;
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if (IS_CHAN_HT40(chan))
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i = rateHt40_0;
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else if (IS_CHAN_HT20(chan))
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i = rateHt20_0;
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ah->regulatory.max_power_level = ratesArray[i];
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if (AR_SREV_9280_10_OR_LATER(ah)) {
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for (i = 0; i < Ar5416RateSize; i++)
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ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
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}
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/* OFDM power per rate */
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
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ATH9K_POW_SM(ratesArray[rate18mb], 24)
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| ATH9K_POW_SM(ratesArray[rate12mb], 16)
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@ -753,19 +765,19 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
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| ATH9K_POW_SM(ratesArray[rate36mb], 8)
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| ATH9K_POW_SM(ratesArray[rate24mb], 0));
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if (IS_CHAN_2GHZ(chan)) {
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
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ATH9K_POW_SM(ratesArray[rate2s], 24)
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| ATH9K_POW_SM(ratesArray[rate2l], 16)
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| ATH9K_POW_SM(ratesArray[rateXr], 8)
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| ATH9K_POW_SM(ratesArray[rate1l], 0));
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
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ATH9K_POW_SM(ratesArray[rate11s], 24)
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| ATH9K_POW_SM(ratesArray[rate11l], 16)
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| ATH9K_POW_SM(ratesArray[rate5_5s], 8)
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| ATH9K_POW_SM(ratesArray[rate5_5l], 0));
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}
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/* CCK power per rate */
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
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ATH9K_POW_SM(ratesArray[rate2s], 24)
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| ATH9K_POW_SM(ratesArray[rate2l], 16)
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| ATH9K_POW_SM(ratesArray[rateXr], 8)
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| ATH9K_POW_SM(ratesArray[rate1l], 0));
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
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ATH9K_POW_SM(ratesArray[rate11s], 24)
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| ATH9K_POW_SM(ratesArray[rate11l], 16)
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| ATH9K_POW_SM(ratesArray[rate5_5s], 8)
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| ATH9K_POW_SM(ratesArray[rate5_5l], 0));
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/* HT20 power per rate */
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
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ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
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| ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
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@ -777,6 +789,7 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
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| ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
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| ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
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/* HT40 power per rate */
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if (IS_CHAN_HT40(chan)) {
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
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ATH9K_POW_SM(ratesArray[rateHt40_3] +
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@ -796,27 +809,12 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
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ht40PowerIncForPdadc, 8)
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| ATH9K_POW_SM(ratesArray[rateHt40_4] +
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ht40PowerIncForPdadc, 0));
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REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
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ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
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| ATH9K_POW_SM(ratesArray[rateExtCck], 16)
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| ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
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| ATH9K_POW_SM(ratesArray[rateDupCck], 0));
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}
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i = rate6mb;
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if (IS_CHAN_HT40(chan))
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i = rateHt40_0;
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else if (IS_CHAN_HT20(chan))
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i = rateHt20_0;
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if (AR_SREV_9280_10_OR_LATER(ah))
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ah->regulatory.max_power_level =
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ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
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else
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ah->regulatory.max_power_level = ratesArray[i];
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}
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static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
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