parisc: Add CPU topology support
Add topology support, including multi-core scheduler support on PA8800/PA8900 CPUs and enhanced output in /proc/cpuinfo, e.g. lscpu now reports on a single-socket, dual-core machine: Architecture: parisc64 CPU(s): 2 On-line CPU(s) list: 0,1 Thread(s) per core: 1 Core(s) per socket: 2 Socket(s): 1 CPU family: PA-RISC 2.0 Model name: PA8800 (Mako) Signed-off-by: Helge Deller <deller@gmx.de>hifive-unleashed-5.1
Helge Deller
parent
05f016d2ca
commit
bf7b4c1b3c
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@ -32,6 +32,7 @@ config PARISC
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select GENERIC_PCI_IOMAP
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select ARCH_HAVE_NMI_SAFE_CMPXCHG
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select GENERIC_SMP_IDLE_THREAD
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select GENERIC_CPU_DEVICES
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select GENERIC_STRNCPY_FROM_USER
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select SYSCTL_ARCH_UNALIGN_ALLOW
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select SYSCTL_EXCEPTION_TRACE
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@ -288,6 +289,21 @@ config SMP
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If you don't know what to do here, say N.
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config PARISC_CPU_TOPOLOGY
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bool "Support cpu topology definition"
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depends on SMP
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default y
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help
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Support PARISC cpu topology definition.
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config SCHED_MC
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bool "Multi-core scheduler support"
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depends on PARISC_CPU_TOPOLOGY && PA8X00
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help
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Multi-core scheduler support improves the CPU scheduler's decision
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making when dealing with multi-core CPU chips at a cost of slightly
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increased overhead in some places. If unsure say N here.
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config IRQSTACKS
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bool "Use separate kernel stacks when processing interrupts"
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default y
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@ -0,0 +1,36 @@
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#ifndef _ASM_PARISC_TOPOLOGY_H
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#define _ASM_PARISC_TOPOLOGY_H
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#ifdef CONFIG_PARISC_CPU_TOPOLOGY
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#include <linux/cpumask.h>
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struct cputopo_parisc {
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int thread_id;
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int core_id;
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int socket_id;
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cpumask_t thread_sibling;
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cpumask_t core_sibling;
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};
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extern struct cputopo_parisc cpu_topology[NR_CPUS];
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#define topology_physical_package_id(cpu) (cpu_topology[cpu].socket_id)
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#define topology_core_id(cpu) (cpu_topology[cpu].core_id)
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#define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling)
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#define topology_sibling_cpumask(cpu) (&cpu_topology[cpu].thread_sibling)
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void init_cpu_topology(void);
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void store_cpu_topology(unsigned int cpuid);
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const struct cpumask *cpu_coregroup_mask(int cpu);
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#else
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static inline void init_cpu_topology(void) { }
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static inline void store_cpu_topology(unsigned int cpuid) { }
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#endif
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#include <asm-generic/topology.h>
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#endif /* _ASM_ARM_TOPOLOGY_H */
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@ -9,8 +9,7 @@ obj-y := cache.o pacache.o setup.o pdt.o traps.o time.o irq.o \
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pa7300lc.o syscall.o entry.o sys_parisc.o firmware.o \
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ptrace.o hardware.o inventory.o drivers.o \
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signal.o hpmc.o real2.o parisc_ksyms.o unaligned.o \
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process.o processor.o pdc_cons.o pdc_chassis.o unwind.o \
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topology.o
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process.o processor.o pdc_cons.o pdc_chassis.o unwind.o
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ifdef CONFIG_FUNCTION_TRACER
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# Do not profile debug and lowlevel utilities
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@ -30,5 +29,6 @@ obj-$(CONFIG_AUDIT) += audit.o
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obj64-$(CONFIG_AUDIT) += compat_audit.o
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# only supported for PCX-W/U in 64-bit mode at the moment
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obj-$(CONFIG_64BIT) += perf.o perf_asm.o $(obj64-y)
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obj-$(CONFIG_PARISC_CPU_TOPOLOGY) += topology.o
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obj-$(CONFIG_FUNCTION_TRACER) += ftrace.o
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obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
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@ -184,6 +184,9 @@ static int __init processor_probe(struct parisc_device *dev)
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p->txn_addr = txn_addr; /* save CPU IRQ address */
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p->cpu_num = cpu_info.cpu_num;
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p->cpu_loc = cpu_info.cpu_loc;
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store_cpu_topology(cpuid);
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#ifdef CONFIG_SMP
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/*
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** FIXME: review if any other initialization is clobbered
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@ -325,6 +328,8 @@ int __init init_per_cpu(int cpunum)
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set_firmware_width();
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ret = pdc_coproc_cfg(&coproc_cfg);
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store_cpu_topology(cpunum);
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if(ret >= 0 && coproc_cfg.ccr_functional) {
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mtctl(coproc_cfg.ccr_functional, 10); /* 10 == Coprocessor Control Reg */
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@ -388,6 +393,14 @@ show_cpuinfo (struct seq_file *m, void *v)
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boot_cpu_data.cpu_hz / 1000000,
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boot_cpu_data.cpu_hz % 1000000 );
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#ifdef CONFIG_PARISC_CPU_TOPOLOGY
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seq_printf(m, "physical id\t: %d\n",
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topology_physical_package_id(cpu));
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seq_printf(m, "siblings\t: %d\n",
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cpumask_weight(topology_core_cpumask(cpu)));
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seq_printf(m, "core id\t\t: %d\n", topology_core_id(cpu));
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#endif
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seq_printf(m, "capabilities\t:");
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if (boot_cpu_data.pdc.capabilities & PDC_MODEL_OS32)
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seq_puts(m, " os32");
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@ -408,6 +408,8 @@ void __init start_parisc(void)
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cpunum = smp_processor_id();
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init_cpu_topology();
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set_firmware_width_unlocked();
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ret = pdc_coproc_cfg_unlocked(&coproc_cfg);
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@ -1,37 +1,142 @@
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/*
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* arch/parisc/kernel/topology.c - Populate sysfs with topology information
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* arch/parisc/kernel/topology.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* Copyright (C) 2017 Helge Deller <deller@gmx.de>
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more
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* details.
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* based on arch/arm/kernel/topology.c
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/cpu.h>
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#include <linux/cache.h>
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#include <linux/percpu.h>
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#include <linux/sched.h>
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#include <linux/sched/topology.h>
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static DEFINE_PER_CPU(struct cpu, cpu_devices);
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#include <asm/topology.h>
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static int __init topology_init(void)
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/*
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* cpu topology table
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*/
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struct cputopo_parisc cpu_topology[NR_CPUS] __read_mostly;
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EXPORT_SYMBOL_GPL(cpu_topology);
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const struct cpumask *cpu_coregroup_mask(int cpu)
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{
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int num;
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for_each_present_cpu(num) {
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register_cpu(&per_cpu(cpu_devices, num), num);
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}
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return 0;
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return &cpu_topology[cpu].core_sibling;
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}
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subsys_initcall(topology_init);
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static void update_siblings_masks(unsigned int cpuid)
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{
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struct cputopo_parisc *cpu_topo, *cpuid_topo = &cpu_topology[cpuid];
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int cpu;
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/* update core and thread sibling masks */
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for_each_possible_cpu(cpu) {
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cpu_topo = &cpu_topology[cpu];
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if (cpuid_topo->socket_id != cpu_topo->socket_id)
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continue;
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cpumask_set_cpu(cpuid, &cpu_topo->core_sibling);
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if (cpu != cpuid)
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cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);
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if (cpuid_topo->core_id != cpu_topo->core_id)
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continue;
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cpumask_set_cpu(cpuid, &cpu_topo->thread_sibling);
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if (cpu != cpuid)
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cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);
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}
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smp_wmb();
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}
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static int dualcores_found __initdata;
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/*
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* store_cpu_topology is called at boot when only one cpu is running
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* and with the mutex cpu_hotplug.lock locked, when several cpus have booted,
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* which prevents simultaneous write access to cpu_topology array
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*/
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void __init store_cpu_topology(unsigned int cpuid)
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{
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struct cputopo_parisc *cpuid_topo = &cpu_topology[cpuid];
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struct cpuinfo_parisc *p;
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int max_socket = -1;
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unsigned long cpu;
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/* If the cpu topology has been already set, just return */
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if (cpuid_topo->core_id != -1)
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return;
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/* create cpu topology mapping */
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cpuid_topo->thread_id = -1;
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cpuid_topo->core_id = 0;
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p = &per_cpu(cpu_data, cpuid);
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for_each_online_cpu(cpu) {
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const struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu);
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if (cpu == cpuid) /* ignore current cpu */
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continue;
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if (cpuinfo->cpu_loc == p->cpu_loc) {
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cpuid_topo->core_id = cpu_topology[cpu].core_id;
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if (p->cpu_loc) {
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cpuid_topo->core_id++;
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cpuid_topo->socket_id = cpu_topology[cpu].socket_id;
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dualcores_found = 1;
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continue;
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}
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}
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if (cpuid_topo->socket_id == -1)
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max_socket = max(max_socket, cpu_topology[cpu].socket_id);
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}
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if (cpuid_topo->socket_id == -1)
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cpuid_topo->socket_id = max_socket + 1;
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update_siblings_masks(cpuid);
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pr_info("CPU%u: thread %d, cpu %d, socket %d\n",
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cpuid, cpu_topology[cpuid].thread_id,
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cpu_topology[cpuid].core_id,
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cpu_topology[cpuid].socket_id);
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}
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static struct sched_domain_topology_level parisc_mc_topology[] = {
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#ifdef CONFIG_SCHED_MC
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{ cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
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#endif
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{ cpu_cpu_mask, SD_INIT_NAME(DIE) },
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{ NULL, },
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};
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/*
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* init_cpu_topology is called at boot when only one cpu is running
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* which prevent simultaneous write access to cpu_topology array
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*/
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void __init init_cpu_topology(void)
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{
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unsigned int cpu;
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/* init core mask and capacity */
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for_each_possible_cpu(cpu) {
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struct cputopo_parisc *cpu_topo = &(cpu_topology[cpu]);
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cpu_topo->thread_id = -1;
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cpu_topo->core_id = -1;
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cpu_topo->socket_id = -1;
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cpumask_clear(&cpu_topo->core_sibling);
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cpumask_clear(&cpu_topo->thread_sibling);
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}
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smp_wmb();
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/* Set scheduler topology descriptor */
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if (dualcores_found)
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set_sched_topology(parisc_mc_topology);
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}
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