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arm64: dts: enable MLB for imx6dl-sabresdauto

Because the pin conflict between fec and mlb, add a
imx6dl-sabreauto-enetirq.dts to avoid the conflict.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Clark Wang 2019-07-03 15:42:09 +08:00 committed by Dong Aisheng
parent fe5efc9cf6
commit bf81727f21
4 changed files with 42 additions and 4 deletions

View File

@ -435,6 +435,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-rex-basic.dtb \
imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabreauto-enetirq.dtb \
imx6dl-sabrelite.dtb \
imx6dl-sabresd.dtb \
imx6dl-savageboard.dtb \

View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2013 Freescale Semiconductor, Inc.
#include "imx6dl-sabreauto.dts"
&fec {
pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
};
&mlb {
status = "disabled";
};

View File

@ -295,8 +295,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
status = "okay";
};
@ -511,6 +509,11 @@
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
>;
};
pinctrl_enet_irq: enetirqgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
@ -636,6 +639,14 @@
>;
};
pinctrl_mlb: mlb {
fsl,pins = <
MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000
MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000
MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000
>;
};
pinctrl_pwm3: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
@ -799,6 +810,12 @@
};
};
&mlb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mlb>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;

View File

@ -330,7 +330,7 @@
clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
<&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
<&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
<&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>,
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
clock-names = "core", "rxtx0",
"rxtx1", "rxtx2",
@ -1061,11 +1061,16 @@
status = "disabled";
};
mlb@218c000 {
mlb: mlb@218c000 {
compatible = "fsl,imx6q-mlb150";
reg = <0x0218c000 0x4000>;
interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
<0 117 IRQ_TYPE_LEVEL_HIGH>,
<0 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_MLB>;
clock-names = "mlb";
iram = <&ocram>;
status = "disabled";
};
usdhc1: usdhc@2190000 {