diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index a638e059135b..c3c6d7d04a76 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -482,6 +482,11 @@ regulator-always-on; }; +/* First two dma channels are reserved on secure omap3 */ +&sdma { + dma-channel-mask = <0xfffffffc>; +}; + &twl { twl_audio: audio { compatible = "ti,twl4030-audio"; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 5698a3e241aa..06d9108a8385 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -206,17 +206,42 @@ reg = <0x48200000 0x1000>; }; - sdma: dma-controller@48056000 { - compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; - reg = <0x48056000 0x1000>; - interrupts = <12>, - <13>, - <14>, - <15>; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <96>; + target-module@48056000 { + compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "dma"; + reg = <0x48056000 0x4>, + <0x4805602c 0x4>, + <0x48056028 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */ + clocks = <&core_l3_ick>; + clock-names = "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48056000 0x1000>; + + sdma: dma-controller@0 { + compatible = "ti,omap3430-sdma", "ti,omap-sdma"; + reg = <0x0 0x1000>; + interrupts = <12>, + <13>, + <14>, + <15>; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <96>; + }; }; gpio1: gpio@48310000 { diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index c618cb257d00..71f3c8f1f924 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -223,6 +223,10 @@ }; }; +&sdma { + compatible = "ti,omap3630-sdma", "ti,omap-sdma"; +}; + /* OMAP3630 needs dss_96m_fck for VENC */ &venc { clocks = <&dss_tv_fck>, <&dss_96m_fck>;