agp/intel: Reinforce the barrier after GTT updates
commit5.4-rM2-2.2.x-imx-squashedf30d3ced9f
upstream. After changing the timing between GTT updates and execution on the GPU, we started seeing sporadic failures on Ironlake. These were narrowed down to being an insufficiently strong enough barrier/delay after updating the GTT and scheduling execution on the GPU. By forcing the uncached read, and adding the missing barrier for the singular insert_page (relocation paths), the sporadic failures go away. Fixes:983d308cb8
("agp/intel: Serialise after GTT updates") Fixes:3497971a71
("agp/intel: Flush chipset writes after updating a single PTE") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Andi Shyti <andi.shyti@intel.com> Cc: stable@vger.kernel.org # v4.0+ Link: https://patchwork.freedesktop.org/patch/msgid/20200410083535.25464-1-chris@chris-wilson.co.uk Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
parent
e81b05e535
commit
bfc12ff905
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@ -846,6 +846,7 @@ void intel_gtt_insert_page(dma_addr_t addr,
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unsigned int flags)
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{
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intel_private.driver->write_entry(addr, pg, flags);
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readl(intel_private.gtt + pg);
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if (intel_private.driver->chipset_flush)
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intel_private.driver->chipset_flush();
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}
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@ -871,7 +872,7 @@ void intel_gtt_insert_sg_entries(struct sg_table *st,
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j++;
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}
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}
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wmb();
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readl(intel_private.gtt + j - 1);
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if (intel_private.driver->chipset_flush)
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intel_private.driver->chipset_flush();
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}
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@ -1105,6 +1106,7 @@ static void i9xx_cleanup(void)
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static void i9xx_chipset_flush(void)
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{
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wmb();
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if (intel_private.i9xx_flush_page)
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writel(1, intel_private.i9xx_flush_page);
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}
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