sh_eth: move data from header file to driver
The driver's header file contains initialized register offset tables which (as any data definitions), of course, have no business being there. Move them to the driver's body, somewhat beautifying the initializers, while at it... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
Sergei Shtylyov
David S. Miller
parent
91f3e7b174
commit
c0013f6f8b
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@ -49,6 +49,224 @@
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NETIF_MSG_RX_ERR| \
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NETIF_MSG_TX_ERR)
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static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
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[EDSR] = 0x0000,
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[EDMR] = 0x0400,
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[EDTRR] = 0x0408,
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[EDRRR] = 0x0410,
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[EESR] = 0x0428,
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[EESIPR] = 0x0430,
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[TDLAR] = 0x0010,
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[TDFAR] = 0x0014,
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[TDFXR] = 0x0018,
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[TDFFR] = 0x001c,
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[RDLAR] = 0x0030,
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[RDFAR] = 0x0034,
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[RDFXR] = 0x0038,
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[RDFFR] = 0x003c,
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[TRSCER] = 0x0438,
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[RMFCR] = 0x0440,
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[TFTR] = 0x0448,
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[FDR] = 0x0450,
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[RMCR] = 0x0458,
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[RPADIR] = 0x0460,
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[FCFTR] = 0x0468,
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[CSMR] = 0x04E4,
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[ECMR] = 0x0500,
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[ECSR] = 0x0510,
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[ECSIPR] = 0x0518,
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[PIR] = 0x0520,
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[PSR] = 0x0528,
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[PIPR] = 0x052c,
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[RFLR] = 0x0508,
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[APR] = 0x0554,
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[MPR] = 0x0558,
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[PFTCR] = 0x055c,
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[PFRCR] = 0x0560,
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[TPAUSER] = 0x0564,
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[GECMR] = 0x05b0,
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[BCULR] = 0x05b4,
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[MAHR] = 0x05c0,
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[MALR] = 0x05c8,
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[TROCR] = 0x0700,
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[CDCR] = 0x0708,
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[LCCR] = 0x0710,
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[CEFCR] = 0x0740,
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[FRECR] = 0x0748,
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[TSFRCR] = 0x0750,
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[TLFRCR] = 0x0758,
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[RFCR] = 0x0760,
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[CERCR] = 0x0768,
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[CEECR] = 0x0770,
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[MAFCR] = 0x0778,
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[RMII_MII] = 0x0790,
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[ARSTR] = 0x0000,
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[TSU_CTRST] = 0x0004,
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[TSU_FWEN0] = 0x0010,
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[TSU_FWEN1] = 0x0014,
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[TSU_FCM] = 0x0018,
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[TSU_BSYSL0] = 0x0020,
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[TSU_BSYSL1] = 0x0024,
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[TSU_PRISL0] = 0x0028,
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[TSU_PRISL1] = 0x002c,
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[TSU_FWSL0] = 0x0030,
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[TSU_FWSL1] = 0x0034,
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[TSU_FWSLC] = 0x0038,
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[TSU_QTAG0] = 0x0040,
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[TSU_QTAG1] = 0x0044,
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[TSU_FWSR] = 0x0050,
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[TSU_FWINMK] = 0x0054,
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[TSU_ADQT0] = 0x0048,
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[TSU_ADQT1] = 0x004c,
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[TSU_VTAG0] = 0x0058,
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[TSU_VTAG1] = 0x005c,
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[TSU_ADSBSY] = 0x0060,
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[TSU_TEN] = 0x0064,
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[TSU_POST1] = 0x0070,
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[TSU_POST2] = 0x0074,
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[TSU_POST3] = 0x0078,
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[TSU_POST4] = 0x007c,
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[TSU_ADRH0] = 0x0100,
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[TSU_ADRL0] = 0x0104,
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[TSU_ADRH31] = 0x01f8,
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[TSU_ADRL31] = 0x01fc,
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[TXNLCR0] = 0x0080,
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[TXALCR0] = 0x0084,
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[RXNLCR0] = 0x0088,
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[RXALCR0] = 0x008c,
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[FWNLCR0] = 0x0090,
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[FWALCR0] = 0x0094,
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[TXNLCR1] = 0x00a0,
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[TXALCR1] = 0x00a0,
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[RXNLCR1] = 0x00a8,
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[RXALCR1] = 0x00ac,
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[FWNLCR1] = 0x00b0,
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[FWALCR1] = 0x00b4,
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};
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static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
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[ECMR] = 0x0100,
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[RFLR] = 0x0108,
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[ECSR] = 0x0110,
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[ECSIPR] = 0x0118,
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[PIR] = 0x0120,
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[PSR] = 0x0128,
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[RDMLR] = 0x0140,
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[IPGR] = 0x0150,
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[APR] = 0x0154,
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[MPR] = 0x0158,
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[TPAUSER] = 0x0164,
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[RFCF] = 0x0160,
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[TPAUSECR] = 0x0168,
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[BCFRR] = 0x016c,
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[MAHR] = 0x01c0,
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[MALR] = 0x01c8,
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[TROCR] = 0x01d0,
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[CDCR] = 0x01d4,
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[LCCR] = 0x01d8,
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[CNDCR] = 0x01dc,
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[CEFCR] = 0x01e4,
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[FRECR] = 0x01e8,
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[TSFRCR] = 0x01ec,
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[TLFRCR] = 0x01f0,
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[RFCR] = 0x01f4,
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[MAFCR] = 0x01f8,
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[RTRATE] = 0x01fc,
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[EDMR] = 0x0000,
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[EDTRR] = 0x0008,
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[EDRRR] = 0x0010,
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[TDLAR] = 0x0018,
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[RDLAR] = 0x0020,
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[EESR] = 0x0028,
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[EESIPR] = 0x0030,
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[TRSCER] = 0x0038,
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[RMFCR] = 0x0040,
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[TFTR] = 0x0048,
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[FDR] = 0x0050,
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[RMCR] = 0x0058,
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[TFUCR] = 0x0064,
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[RFOCR] = 0x0068,
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[FCFTR] = 0x0070,
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[RPADIR] = 0x0078,
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[TRIMD] = 0x007c,
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[RBWAR] = 0x00c8,
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[RDFAR] = 0x00cc,
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[TBRAR] = 0x00d4,
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[TDFAR] = 0x00d8,
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};
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static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
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[ECMR] = 0x0160,
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[ECSR] = 0x0164,
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[ECSIPR] = 0x0168,
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[PIR] = 0x016c,
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[MAHR] = 0x0170,
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[MALR] = 0x0174,
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[RFLR] = 0x0178,
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[PSR] = 0x017c,
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[TROCR] = 0x0180,
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[CDCR] = 0x0184,
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[LCCR] = 0x0188,
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[CNDCR] = 0x018c,
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[CEFCR] = 0x0194,
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[FRECR] = 0x0198,
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[TSFRCR] = 0x019c,
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[TLFRCR] = 0x01a0,
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[RFCR] = 0x01a4,
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[MAFCR] = 0x01a8,
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[IPGR] = 0x01b4,
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[APR] = 0x01b8,
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[MPR] = 0x01bc,
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[TPAUSER] = 0x01c4,
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[BCFR] = 0x01cc,
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[ARSTR] = 0x0000,
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[TSU_CTRST] = 0x0004,
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[TSU_FWEN0] = 0x0010,
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[TSU_FWEN1] = 0x0014,
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[TSU_FCM] = 0x0018,
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[TSU_BSYSL0] = 0x0020,
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[TSU_BSYSL1] = 0x0024,
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[TSU_PRISL0] = 0x0028,
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[TSU_PRISL1] = 0x002c,
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[TSU_FWSL0] = 0x0030,
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[TSU_FWSL1] = 0x0034,
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[TSU_FWSLC] = 0x0038,
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[TSU_QTAGM0] = 0x0040,
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[TSU_QTAGM1] = 0x0044,
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[TSU_ADQT0] = 0x0048,
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[TSU_ADQT1] = 0x004c,
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[TSU_FWSR] = 0x0050,
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[TSU_FWINMK] = 0x0054,
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[TSU_ADSBSY] = 0x0060,
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[TSU_TEN] = 0x0064,
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[TSU_POST1] = 0x0070,
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[TSU_POST2] = 0x0074,
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[TSU_POST3] = 0x0078,
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[TSU_POST4] = 0x007c,
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[TXNLCR0] = 0x0080,
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[TXALCR0] = 0x0084,
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[RXNLCR0] = 0x0088,
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[RXALCR0] = 0x008c,
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[FWNLCR0] = 0x0090,
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[FWALCR0] = 0x0094,
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[TXNLCR1] = 0x00a0,
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[TXALCR1] = 0x00a0,
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[RXNLCR1] = 0x00a8,
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[RXALCR1] = 0x00ac,
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[FWNLCR1] = 0x00b0,
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[FWALCR1] = 0x00b4,
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[TSU_ADRH0] = 0x0100,
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[TSU_ADRL0] = 0x0104,
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[TSU_ADRL31] = 0x01fc,
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};
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#if defined(CONFIG_CPU_SUBTYPE_SH7734) || \
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defined(CONFIG_CPU_SUBTYPE_SH7763) || \
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defined(CONFIG_ARCH_R8A7740)
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@ -156,225 +156,6 @@ enum {
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SH_ETH_MAX_REGISTER_OFFSET,
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};
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static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
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[EDSR] = 0x0000,
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[EDMR] = 0x0400,
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[EDTRR] = 0x0408,
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[EDRRR] = 0x0410,
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[EESR] = 0x0428,
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[EESIPR] = 0x0430,
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[TDLAR] = 0x0010,
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[TDFAR] = 0x0014,
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[TDFXR] = 0x0018,
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[TDFFR] = 0x001c,
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[RDLAR] = 0x0030,
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[RDFAR] = 0x0034,
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[RDFXR] = 0x0038,
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[RDFFR] = 0x003c,
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[TRSCER] = 0x0438,
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[RMFCR] = 0x0440,
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[TFTR] = 0x0448,
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[FDR] = 0x0450,
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[RMCR] = 0x0458,
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[RPADIR] = 0x0460,
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[FCFTR] = 0x0468,
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[CSMR] = 0x04E4,
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[ECMR] = 0x0500,
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[ECSR] = 0x0510,
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[ECSIPR] = 0x0518,
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[PIR] = 0x0520,
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[PSR] = 0x0528,
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[PIPR] = 0x052c,
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[RFLR] = 0x0508,
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[APR] = 0x0554,
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[MPR] = 0x0558,
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[PFTCR] = 0x055c,
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[PFRCR] = 0x0560,
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[TPAUSER] = 0x0564,
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[GECMR] = 0x05b0,
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[BCULR] = 0x05b4,
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[MAHR] = 0x05c0,
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[MALR] = 0x05c8,
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[TROCR] = 0x0700,
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[CDCR] = 0x0708,
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[LCCR] = 0x0710,
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[CEFCR] = 0x0740,
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[FRECR] = 0x0748,
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[TSFRCR] = 0x0750,
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[TLFRCR] = 0x0758,
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[RFCR] = 0x0760,
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[CERCR] = 0x0768,
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[CEECR] = 0x0770,
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[MAFCR] = 0x0778,
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[RMII_MII] = 0x0790,
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[ARSTR] = 0x0000,
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[TSU_CTRST] = 0x0004,
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[TSU_FWEN0] = 0x0010,
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[TSU_FWEN1] = 0x0014,
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[TSU_FCM] = 0x0018,
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[TSU_BSYSL0] = 0x0020,
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[TSU_BSYSL1] = 0x0024,
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[TSU_PRISL0] = 0x0028,
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[TSU_PRISL1] = 0x002c,
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[TSU_FWSL0] = 0x0030,
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[TSU_FWSL1] = 0x0034,
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[TSU_FWSLC] = 0x0038,
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[TSU_QTAG0] = 0x0040,
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[TSU_QTAG1] = 0x0044,
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[TSU_FWSR] = 0x0050,
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[TSU_FWINMK] = 0x0054,
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[TSU_ADQT0] = 0x0048,
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[TSU_ADQT1] = 0x004c,
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[TSU_VTAG0] = 0x0058,
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[TSU_VTAG1] = 0x005c,
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[TSU_ADSBSY] = 0x0060,
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[TSU_TEN] = 0x0064,
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[TSU_POST1] = 0x0070,
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[TSU_POST2] = 0x0074,
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[TSU_POST3] = 0x0078,
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[TSU_POST4] = 0x007c,
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[TSU_ADRH0] = 0x0100,
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[TSU_ADRL0] = 0x0104,
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[TSU_ADRH31] = 0x01f8,
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[TSU_ADRL31] = 0x01fc,
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[TXNLCR0] = 0x0080,
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[TXALCR0] = 0x0084,
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[RXNLCR0] = 0x0088,
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[RXALCR0] = 0x008c,
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[FWNLCR0] = 0x0090,
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[FWALCR0] = 0x0094,
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[TXNLCR1] = 0x00a0,
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[TXALCR1] = 0x00a0,
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[RXNLCR1] = 0x00a8,
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[RXALCR1] = 0x00ac,
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[FWNLCR1] = 0x00b0,
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[FWALCR1] = 0x00b4,
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};
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static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
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[ECMR] = 0x0100,
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[RFLR] = 0x0108,
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[ECSR] = 0x0110,
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[ECSIPR] = 0x0118,
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[PIR] = 0x0120,
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[PSR] = 0x0128,
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[RDMLR] = 0x0140,
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[IPGR] = 0x0150,
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[APR] = 0x0154,
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[MPR] = 0x0158,
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[TPAUSER] = 0x0164,
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[RFCF] = 0x0160,
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[TPAUSECR] = 0x0168,
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[BCFRR] = 0x016c,
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[MAHR] = 0x01c0,
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[MALR] = 0x01c8,
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[TROCR] = 0x01d0,
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[CDCR] = 0x01d4,
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[LCCR] = 0x01d8,
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[CNDCR] = 0x01dc,
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[CEFCR] = 0x01e4,
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[FRECR] = 0x01e8,
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[TSFRCR] = 0x01ec,
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[TLFRCR] = 0x01f0,
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[RFCR] = 0x01f4,
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[MAFCR] = 0x01f8,
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[RTRATE] = 0x01fc,
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[EDMR] = 0x0000,
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[EDTRR] = 0x0008,
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[EDRRR] = 0x0010,
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[TDLAR] = 0x0018,
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[RDLAR] = 0x0020,
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[EESR] = 0x0028,
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[EESIPR] = 0x0030,
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[TRSCER] = 0x0038,
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[RMFCR] = 0x0040,
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[TFTR] = 0x0048,
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[FDR] = 0x0050,
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[RMCR] = 0x0058,
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[TFUCR] = 0x0064,
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[RFOCR] = 0x0068,
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[FCFTR] = 0x0070,
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[RPADIR] = 0x0078,
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[TRIMD] = 0x007c,
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[RBWAR] = 0x00c8,
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[RDFAR] = 0x00cc,
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[TBRAR] = 0x00d4,
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[TDFAR] = 0x00d8,
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};
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static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
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[ECMR] = 0x0160,
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[ECSR] = 0x0164,
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[ECSIPR] = 0x0168,
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[PIR] = 0x016c,
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[MAHR] = 0x0170,
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[MALR] = 0x0174,
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[RFLR] = 0x0178,
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[PSR] = 0x017c,
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[TROCR] = 0x0180,
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[CDCR] = 0x0184,
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[LCCR] = 0x0188,
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[CNDCR] = 0x018c,
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[CEFCR] = 0x0194,
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[FRECR] = 0x0198,
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[TSFRCR] = 0x019c,
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[TLFRCR] = 0x01a0,
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[RFCR] = 0x01a4,
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[MAFCR] = 0x01a8,
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[IPGR] = 0x01b4,
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[APR] = 0x01b8,
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[MPR] = 0x01bc,
|
||||
[TPAUSER] = 0x01c4,
|
||||
[BCFR] = 0x01cc,
|
||||
|
||||
[ARSTR] = 0x0000,
|
||||
[TSU_CTRST] = 0x0004,
|
||||
[TSU_FWEN0] = 0x0010,
|
||||
[TSU_FWEN1] = 0x0014,
|
||||
[TSU_FCM] = 0x0018,
|
||||
[TSU_BSYSL0] = 0x0020,
|
||||
[TSU_BSYSL1] = 0x0024,
|
||||
[TSU_PRISL0] = 0x0028,
|
||||
[TSU_PRISL1] = 0x002c,
|
||||
[TSU_FWSL0] = 0x0030,
|
||||
[TSU_FWSL1] = 0x0034,
|
||||
[TSU_FWSLC] = 0x0038,
|
||||
[TSU_QTAGM0] = 0x0040,
|
||||
[TSU_QTAGM1] = 0x0044,
|
||||
[TSU_ADQT0] = 0x0048,
|
||||
[TSU_ADQT1] = 0x004c,
|
||||
[TSU_FWSR] = 0x0050,
|
||||
[TSU_FWINMK] = 0x0054,
|
||||
[TSU_ADSBSY] = 0x0060,
|
||||
[TSU_TEN] = 0x0064,
|
||||
[TSU_POST1] = 0x0070,
|
||||
[TSU_POST2] = 0x0074,
|
||||
[TSU_POST3] = 0x0078,
|
||||
[TSU_POST4] = 0x007c,
|
||||
|
||||
[TXNLCR0] = 0x0080,
|
||||
[TXALCR0] = 0x0084,
|
||||
[RXNLCR0] = 0x0088,
|
||||
[RXALCR0] = 0x008c,
|
||||
[FWNLCR0] = 0x0090,
|
||||
[FWALCR0] = 0x0094,
|
||||
[TXNLCR1] = 0x00a0,
|
||||
[TXALCR1] = 0x00a0,
|
||||
[RXNLCR1] = 0x00a8,
|
||||
[RXALCR1] = 0x00ac,
|
||||
[FWNLCR1] = 0x00b0,
|
||||
[FWALCR1] = 0x00b4,
|
||||
|
||||
[TSU_ADRH0] = 0x0100,
|
||||
[TSU_ADRL0] = 0x0104,
|
||||
[TSU_ADRL31] = 0x01fc,
|
||||
|
||||
};
|
||||
|
||||
/* Driver's parameters */
|
||||
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
|
||||
#define SH4_SKB_RX_ALIGN 32
|
||||
|
|
|
|||
Loading…
Reference in New Issue