ARM: 6379/1: Assume new page cache pages have dirty D-cache
There are places in Linux where writes to newly allocated page cache pages happen without a subsequent call to flush_dcache_page() (several PIO drivers including USB HCD). This patch changes the meaning of PG_arch_1 to be PG_dcache_clean and always flush the D-cache for a newly mapped page in update_mmu_cache(). The patch also sets the PG_arch_1 bit in the DMA cache maintenance function to avoid additional cache flushing in update_mmu_cache(). Tested-by: Rabin Vincent <rabin.vincent@stericsson.com> Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -137,10 +137,10 @@
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#endif
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/*
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* This flag is used to indicate that the page pointed to by a pte
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* is dirty and requires cleaning before returning it to the user.
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* This flag is used to indicate that the page pointed to by a pte is clean
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* and does not require cleaning before returning it to the user.
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*/
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#define PG_dcache_dirty PG_arch_1
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#define PG_dcache_clean PG_arch_1
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/*
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* MM Cache Management
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@ -560,7 +560,7 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
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#endif
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/*
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* if PG_dcache_dirty is set for the page, we need to ensure that any
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* If PG_dcache_clean is not set for the page, we need to ensure that any
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* cache entries for the kernels virtual memory range are written
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* back to the page.
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*/
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@ -73,7 +73,7 @@ void v4_mc_copy_user_highpage(struct page *to, struct page *from,
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{
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void *kto = kmap_atomic(to, KM_USER1);
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if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
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if (!test_and_set_bit(PG_dcache_clean, &from->flags))
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__flush_dcache_page(page_mapping(from), from);
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spin_lock(&minicache_lock);
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@ -79,7 +79,7 @@ static void v6_copy_user_highpage_aliasing(struct page *to,
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unsigned int offset = CACHE_COLOUR(vaddr);
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unsigned long kfrom, kto;
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if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
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if (!test_and_set_bit(PG_dcache_clean, &from->flags))
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__flush_dcache_page(page_mapping(from), from);
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/* FIXME: not highmem safe */
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@ -95,7 +95,7 @@ void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
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{
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void *kto = kmap_atomic(to, KM_USER1);
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if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
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if (!test_and_set_bit(PG_dcache_clean, &from->flags))
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__flush_dcache_page(page_mapping(from), from);
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spin_lock(&minicache_lock);
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@ -523,6 +523,12 @@ void ___dma_page_dev_to_cpu(struct page *page, unsigned long off,
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outer_inv_range(paddr, paddr + size);
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dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
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/*
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* Mark the D-cache clean for this page to avoid extra flushing.
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*/
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if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
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set_bit(PG_dcache_clean, &page->flags);
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}
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EXPORT_SYMBOL(___dma_page_dev_to_cpu);
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@ -141,7 +141,7 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
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* a page table, or changing an existing PTE. Basically, there are two
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* things that we need to take care of:
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*
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* 1. If PG_dcache_dirty is set for the page, we need to ensure
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* 1. If PG_dcache_clean is not set for the page, we need to ensure
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* that any cache entries for the kernels virtual memory
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* range are written back to the page.
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* 2. If we have multiple shared mappings of the same space in
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@ -169,7 +169,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
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mapping = page_mapping(page);
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#ifndef CONFIG_SMP
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if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
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if (!test_and_set_bit(PG_dcache_clean, &page->flags))
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__flush_dcache_page(mapping, page);
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#endif
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if (mapping) {
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@ -248,7 +248,7 @@ void flush_dcache_page(struct page *page)
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#ifndef CONFIG_SMP
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if (mapping && !mapping_mapped(mapping))
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set_bit(PG_dcache_dirty, &page->flags);
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clear_bit(PG_dcache_clean, &page->flags);
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else
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#endif
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{
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@ -257,6 +257,7 @@ void flush_dcache_page(struct page *page)
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__flush_dcache_aliases(mapping, page);
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else if (mapping)
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__flush_icache_all();
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set_bit(PG_dcache_clean, &page->flags);
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}
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}
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EXPORT_SYMBOL(flush_dcache_page);
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