Merge remote-tracking branch 'origin/dma/edma' into dma/next

* origin/dma/edma: (23 commits)
  MLK-22909 dmaengine: fsl-edma-v3: clear interrupt coming after channel terminated
  MLK-22302-2: dmaengine: fsl-edma-v3: fix build warning with CONFIG_PM_SLEEP=n
  MLK-22284-2 dmaengine: fsl-edma-v3: check dma description before register touch
  MLK-22284-1 dmaengine: fsl-edma-v3: add power domains for each channel
  MLK-21443: dmaengine: fsl-edma-v3: clear pending irq before request irq
  ...

Documentation/devicetree/bindings/dma/fsl-edma-v3.txt

@@ -0,0 +1,82 @@
+* Freescale enhanced Direct Memory Access(eDMA-v3) Controller
+
+  The eDMA-v3 controller is inherited from FSL eDMA, and firstly is intergrated
+  on Freescale i.MX8QM SOC chip. The eDMA channels have multiplex capability by
+  programmble memory-mapped registers. Specific DMA request source has fixed channel.
+
+* eDMA Controller
+Required properties:
+- compatible :
+	- "fsl,imx8qm-edma" for eDMA used similar to that on i.MX8QM SoC
+	- "fsl,imx8qm-adma" for audio eDMA used on i.MX8QM
+- reg : Specifies base physical address(s) and size of the eDMA channel registers.
+	Each eDMA channel has separated register's address and size.
+- interrupts : A list of interrupt-specifiers, each channel has one interrupt.
+- interrupt-names : Should contain below template:
+	"edmaX-chanX-Xx"
+	     |     | |---> receive/transmit, r or t
+	     |     |---> channel id, the max number is 32
+	     |---> edma controller instance, 0, 1, 2,..etc
+
+- #dma-cells : Must be <3>.
+	The 1st cell specifies the channel ID.
+	The 2nd cell specifies the channel priority.
+	The 3rd cell specifies the channel attributes which include below:
+	BIT(0): transmit or receive:
+		0: transmit, 1: receive.
+	BIT(1): local or remote access:
+		0: local, 1: remote.
+	BIT(2): dualfifo case or not(only in Audio cyclic now):
+		0: not dual fifo case, 1: dualfifo case.
+	See the SoC's reference manual for all the supported request sources.
+- dma-channels : Number of channels supported by the controller
+- power-domains: Power domains for edma channel used.
+- power-domain-names: Power domains name for edma channel used.
+
+Examples:
+edma0: dma-controller@40018000 {
+	compatible = "fsl,imx8qm-edma";
+	reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */
+	      <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */
+	      <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
+	      <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */
+	#dma-cells = <3>;
+	dma-channels = <4>;
+	interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx",
+			  "edma0-chan14-rx", "edma0-chan15-tx";
+	power-domains = <&pd IMX_SC_R_DMA_0_CH12>,
+			<&pd IMX_SC_R_DMA_0_CH13>,
+			<&pd IMX_SC_R_DMA_0_CH14>,
+			<&pd IMX_SC_R_DMA_0_CH15>;
+	power-domain-names = "edma0-chan12", "edma0-chan13",
+			     "edma0-chan14", "edma0-chan15";
+	status = "okay";
+};
+
+* DMA clients
+DMA client drivers that uses the DMA function must use the format described
+in the dma.txt file, using a three-cell specifier for each channel: the 1st
+specifies the channel number, the 2nd specifies the priority, and the 3rd
+specifies the channel type is for transmit or receive: 0: transmit, 1: receive.
+
+Examples:
+lpuart1: serial@5a070000 {
+	compatible = "fsl,imx8qm-lpuart";
+	reg = <0x0 0x5a070000 0x0 0x1000>;
+	interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-parent = <&gic>;
+	clocks = <&clk IMX8QM_UART1_CLK>;
+	clock-names = "ipg";
+	assigned-clock-names = <&clk IMX8QM_UART1_CLK>;
+	assigned-clock-rates = <80000000>;
+	power-domains = <&pd IMX_SC_R_UART_1>,
+	power-domain-names = "uart";
+	dma-names = "tx","rx";
+	dmas = <&edma0 15 0 0>,
+		<&edma0 14 0 1>;
+	status = "disabled";
+};

Documentation/devicetree/bindings/dma/fsl-imx-dma.txt

@@ -16,6 +16,21 @@ Optional properties:
 - #dma-channels : Number of DMA channels supported. Should be 16.
 - #dma-requests : Number of DMA requests supported.
 
+* DMA capability limitation
+
+Specify the DMA capability limitations.
+For example, some SoCs only support up to 32bit DMA capability, although
+they are 64bit SoCs.
+
+- only-dma-mask32: 1 means that the SoCs only suppot up to 32bit DMA
+  capability.
+
+Example:
+	dma_cap: dma_cap {
+		compatible = "dma-capability";
+		only-dma-mask32 = <1>;
+	};
+
 Example:
 
 	dma: dma@10001000 {

drivers/dma/Kconfig

@@ -245,6 +245,17 @@ config FSL_QDMA
          or dequeuing DMA jobs from, different work queues.
          This module can be found on NXP Layerscape SoCs.
 	  The qdma driver only work on  SoCs with a DPAA hardware block.
+config FSL_EDMA_V3
+	tristate "Freescale eDMA v3 engine support"
+	depends on OF
+	select DMA_ENGINE
+	select DMA_VIRTUAL_CHANNELS
+	help
+	  Support the Freescale eDMA v3 engine with programmable channel.
+	  This driver is based on FSL_EDMA but big changes come such as
+	  different interrupt for different channel, different register
+	  scope for different channel.
+	  This module can be found on Freescale i.MX8QM.
 
 config FSL_RAID
         tristate "Freescale RAID engine Support"

drivers/dma/Makefile

@@ -32,6 +32,7 @@ obj-$(CONFIG_DW_EDMA) += dw-edma/
 obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
 obj-$(CONFIG_FSL_DMA) += fsldma.o
 obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
+obj-$(CONFIG_FSL_EDMA_V3) += fsl-edma-v3.o
 obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o
 obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
 obj-$(CONFIG_FSL_RAID) += fsl_raid.o

drivers/dma/fsl-edma-common.c

@@ -305,6 +305,11 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
 	return len;
 }
 
+void fsl_edma_get_realcnt(struct fsl_edma_chan *fsl_chan)
+{
+	fsl_chan->chn_real_count = fsl_edma_desc_residue(fsl_chan, NULL, true);
+}
+
 enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
 		dma_cookie_t cookie, struct dma_tx_state *txstate)
 {
@@ -314,8 +319,12 @@ enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
 	unsigned long flags;
 
 	status = dma_cookie_status(chan, cookie, txstate);
-	if (status == DMA_COMPLETE)
+	if (status == DMA_COMPLETE) {
+		spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
+		txstate->residue = fsl_chan->chn_real_count;
+		spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 		return status;
+	}
 
 	if (!txstate)
 		return fsl_chan->status;

drivers/dma/fsl-edma-common.h

@@ -126,6 +126,7 @@ struct fsl_edma_chan {
 	u32				dma_dev_size;
 	enum dma_data_direction		dma_dir;
 	char				chan_name[16];
+	u32				chn_real_count;
 };
 
 struct fsl_edma_desc {
@@ -229,6 +230,7 @@ int fsl_edma_pause(struct dma_chan *chan);
 int fsl_edma_resume(struct dma_chan *chan);
 int fsl_edma_slave_config(struct dma_chan *chan,
 				 struct dma_slave_config *cfg);
+void fsl_edma_get_realcnt(struct fsl_edma_chan *fsl_chan);
 enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
 		dma_cookie_t cookie, struct dma_tx_state *txstate);
 struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(

drivers/dma/fsl-edma.c

@@ -46,6 +46,7 @@ static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
 
 			spin_lock(&fsl_chan->vchan.lock);
 			if (!fsl_chan->edesc->iscyclic) {
+				fsl_edma_get_realcnt(fsl_chan);
 				list_del(&fsl_chan->edesc->vdesc.node);
 				vchan_cookie_complete(&fsl_chan->edesc->vdesc);
 				fsl_chan->edesc = NULL;