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ARM: dts: r7s72100: Correct watchdog timer interrupt type 

According to table 7.3 ("List of Interrupt IDs") in the RZ/A1H Hardware
User's Manual rev. 3.00, the watchdog timer interrupt is a level
interrupt.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
hifive-unleashed-5.1
Geert Uytterhoeven 2018-05-07 15:24:48 +02:00 committed by Simon Horman
parent 7207b94754
commit c02cc235a2
1 changed files with 1 additions and 1 deletions
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2
arch/arm/boot/dts/r7s72100.dtsi
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@ -387,7 +387,7 @@
wdt: watchdog@fcfe0000 {
compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
reg = <0xfcfe0000 0x6>;
interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&p0_clk>;
};