drm/i915: s/PUNIT_REG_DSPFREQ/PUNIT_REG_DSPSSPM/
Rename the punit display power register to match the spec. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181129175504.3630-1-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
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@ -1044,7 +1044,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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/* See configdb bunit SB addr map */
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#define BUNIT_REG_BISOC 0x11
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#define PUNIT_REG_DSPFREQ 0x36
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#define PUNIT_REG_DSPSSPM 0x36
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#define DSPFREQSTAT_SHIFT_CHV 24
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#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
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#define DSPFREQGUAR_SHIFT_CHV 8
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@ -468,7 +468,7 @@ static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
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cdclk_state->vco);
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mutex_lock(&dev_priv->pcu_lock);
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val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
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val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
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mutex_unlock(&dev_priv->pcu_lock);
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if (IS_VALLEYVIEW(dev_priv))
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@ -543,11 +543,11 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
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wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
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mutex_lock(&dev_priv->pcu_lock);
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val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
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val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
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val &= ~DSPFREQGUAR_MASK;
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val |= (cmd << DSPFREQGUAR_SHIFT);
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vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
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if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
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vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
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if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
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DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
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50)) {
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DRM_ERROR("timed out waiting for CDclk change\n");
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@ -624,11 +624,11 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
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wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
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mutex_lock(&dev_priv->pcu_lock);
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val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
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val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
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val &= ~DSPFREQGUAR_MASK_CHV;
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val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
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vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
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if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
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vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
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if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
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DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
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50)) {
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DRM_ERROR("timed out waiting for CDclk change\n");
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@ -335,12 +335,12 @@ static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
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mutex_lock(&dev_priv->pcu_lock);
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val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
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val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
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if (enable)
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val |= DSP_MAXFIFO_PM5_ENABLE;
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else
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val &= ~DSP_MAXFIFO_PM5_ENABLE;
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vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
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vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
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mutex_unlock(&dev_priv->pcu_lock);
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}
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@ -6063,7 +6063,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
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if (IS_CHERRYVIEW(dev_priv)) {
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mutex_lock(&dev_priv->pcu_lock);
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val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
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val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
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if (val & DSP_MAXFIFO_PM5_ENABLE)
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wm->level = VLV_WM_LEVEL_PM5;
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@ -1760,7 +1760,7 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
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mutex_lock(&dev_priv->pcu_lock);
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state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
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state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);
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/*
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* We only ever set the power-on and power-gate states, anything
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* else is unexpected.
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@ -1772,7 +1772,7 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
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* A transient state at this point would mean some unexpected party
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* is poking at the power controls too.
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*/
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ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
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ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);
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WARN_ON(ctrl << 16 != state);
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mutex_unlock(&dev_priv->pcu_lock);
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@ -1793,20 +1793,20 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
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mutex_lock(&dev_priv->pcu_lock);
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#define COND \
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((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
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((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state)
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if (COND)
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goto out;
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ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
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ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
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ctrl &= ~DP_SSC_MASK(pipe);
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ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
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vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
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vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl);
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if (wait_for(COND, 100))
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DRM_ERROR("timeout setting power well state %08x (%08x)\n",
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state,
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vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
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vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM));
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#undef COND
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