drm/i915: Move Braswell stop_machine GGTT insertion workaround
There was a silent conflict between commit0a87871626
Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu Oct 15 14:23:01 2015 +0200 drm/i915: restore ggtt double-bind avoidance and commit5bab6f60cb
Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Fri Oct 23 18:43:32 2015 +0100 drm/i915: Serialise updates to GGTT with access through GGTT on Braswell thankfully caught by the extra WARN safegaurd in0a878716
. Since we now override the GGTT insert_pages callback when installing the aliasing ppgtt, we assert that the callback is the original ggtt routine. However, on Braswell we now use a different insertion routine to serialise access through the GGTT with updating the PTE and hence the conflict. To avoid the conflict, move the custom insertion routine for Braswell down a level. Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1447859979-20107-1-git-send-email-chris@chris-wilson.co.uk Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: drm-intel-fixes@lists.freedesktop.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -2384,6 +2384,32 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
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assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
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}
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struct insert_entries {
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struct i915_address_space *vm;
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struct sg_table *st;
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uint64_t start;
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enum i915_cache_level level;
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u32 flags;
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};
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static int gen8_ggtt_insert_entries__cb(void *_arg)
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{
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struct insert_entries *arg = _arg;
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gen8_ggtt_insert_entries(arg->vm, arg->st,
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arg->start, arg->level, arg->flags);
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return 0;
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}
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static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm,
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struct sg_table *st,
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uint64_t start,
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enum i915_cache_level level,
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u32 flags)
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{
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struct insert_entries arg = { vm, st, start, level, flags };
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stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL);
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}
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/*
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* Binds an object into the global gtt with the specified cache level. The object
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* will be accessible to the GPU via commands whose operands reference offsets
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@ -2560,26 +2586,6 @@ static int ggtt_bind_vma(struct i915_vma *vma,
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return 0;
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}
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struct ggtt_bind_vma__cb {
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struct i915_vma *vma;
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enum i915_cache_level cache_level;
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u32 flags;
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};
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static int ggtt_bind_vma__cb(void *_arg)
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{
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struct ggtt_bind_vma__cb *arg = _arg;
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return ggtt_bind_vma(arg->vma, arg->cache_level, arg->flags);
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}
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static int ggtt_bind_vma__BKL(struct i915_vma *vma,
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enum i915_cache_level cache_level,
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u32 flags)
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{
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struct ggtt_bind_vma__cb arg = { vma, cache_level, flags };
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return stop_machine(ggtt_bind_vma__cb, &arg, NULL);
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}
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static int aliasing_gtt_bind_vma(struct i915_vma *vma,
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enum i915_cache_level cache_level,
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u32 flags)
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@ -3048,8 +3054,8 @@ static int gen8_gmch_probe(struct drm_device *dev,
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dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
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dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
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if (IS_CHERRYVIEW(dev))
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dev_priv->gtt.base.bind_vma = ggtt_bind_vma__BKL;
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if (IS_CHERRYVIEW(dev_priv))
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dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries__BKL;
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return ret;
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}
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