asm-generic fixes for v4.17-rc1
I have one regression fix for a minor build problem after the architecture removal series, plus a rework of the barriers in the readl/writel functions, thanks to work by Sinan Kaya: This started from a discussion on the linuxpcc and rdma mailing lists [1]. To summarize, we decided that architectures are responsible to serialize readl() and writel() accesses on a device MMIO space relative to DMA performed by that device. This series provides a pessimistic implementation of that behavior for asm-generic/io.h, which is in turn used by a number of architectures (h8300, microblaze, nios2, openrisc, s390, sparc, um, unicore32, and xtensa). Some of those presumably need no extra barriers, or something weaker than rmb()/wmb(), and they are advised to override the new default for better performance. For inb()/outb(), the same barriers are used, but architectures might want to add another barrier to outb() here if that can guarantee non-posted behavior (some architectures can, others cannot do that). The readl_relaxed()/writel_relaxed() family of functions retains the existing behavior with no extra barriers. [1]: https://lists.ozlabs.org/pipermail/linuxppc-dev/2018-March/170481.html -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJazitHAAoJEGCrR//JCVInd0wP/iMzr1HWDgMjeeuxekFjwWDg 9fL+BFt1afeYb4wniqJcF7ymLow/H5Fbhj4dwM1p34De+CZ3+3JGNyK8qzoeKPjR I2U5QqjWCHWDqpWRGWxO28dbs5/1EoW1zgctTNMUPHiamnomz9XIn0xaVKpu4HZ3 OtaeJm8seKTSj1+A2fye9sDpqMUJuVcnZAWJgqMJ8T98uMBOiJYWHftnFEJpSlwG SJSt4AYsJnE+3BFawX1g3VWrHn9WN1uwVasJ1INFkLYNuLMYaK7RYjoBWNwHW+RQ luq4xZE+HZehyZptilfs05x2IlhGSOVN5m0nVM2if9aXoEoO1UdaySbwO6Ukq085 VyfCzY+k4l0v44o4JqaSyAFLEae0809E6cQcGg3cjdstQv1Q3cgAJ96myP0x+QTw b0xJGoo46eOfqpK4njARyjTSceYPgzkB5Dqngg9rCuh+EogotWpRRDB6zoeGGRK8 oOzMp0qLsAZFcYvjft5h0Cp6X51qfyJpBkJkvnASmF4yJPZlpCRGux+HM3jFb9bV zbH+KPqTa47OmOK8MNIaFHMR1yMgZU6B2oEwFDEaG0M+6FC5irMSkgcDwIIMJXlJ wLp7+4WhwFzFDe1mp/tKM5V4h9D6vQtSUjgOJffhxRXqCMkxc7eABmYBBkjMCsca ibKXyZN16d1kRU9j7upb =oBQh -----END PGP SIGNATURE----- Merge tag 'asm-generic' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic Pull asm-generic fixes from Arnd Bergmann: "I have one regression fix for a minor build problem after the architecture removal series, plus a rework of the barriers in the readl/writel functions, thanks to work by Sinan Kaya: This started from a discussion on the linuxpcc and rdma mailing lists[1]. To summarize, we decided that architectures are responsible to serialize readl() and writel() accesses on a device MMIO space relative to DMA performed by that device. This series provides a pessimistic implementation of that behavior for asm-generic/io.h, which is in turn used by a number of architectures (h8300, microblaze, nios2, openrisc, s390, sparc, um, unicore32, and xtensa). Some of those presumably need no extra barriers, or something weaker than rmb()/wmb(), and they are advised to override the new default for better performance. For inb()/outb(), the same barriers are used, but architectures might want to add another barrier to outb() here if that can guarantee non-posted behavior (some architectures can, others cannot do that). The readl_relaxed()/writel_relaxed() family of functions retains the existing behavior with no extra barriers" [1] https://lists.ozlabs.org/pipermail/linuxppc-dev/2018-March/170481.html * tag 'asm-generic' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: io: change writeX_relaxed() to remove barriers io: change readX_relaxed() to remove barriers dts: remove cris & metag dts hard link file io: change inX() to have their own IO barrier overrides io: change outX() to have their own IO barrier overrides io: define stronger ordering for the default writeX() implementation io: define stronger ordering for the default readX() implementation io: define several IO & PIO barrier types for the asm-generic versionhifive-unleashed-5.1
Linus Torvalds
commit
c17b0aadb7
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@ -25,6 +25,50 @@
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#define mmiowb() do {} while (0)
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#endif
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#ifndef __io_br
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#define __io_br() barrier()
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#endif
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/* prevent prefetching of coherent DMA data ahead of a dma-complete */
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#ifndef __io_ar
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#ifdef rmb
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#define __io_ar() rmb()
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#else
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#define __io_ar() barrier()
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#endif
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#endif
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/* flush writes to coherent DMA data before possibly triggering a DMA read */
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#ifndef __io_bw
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#ifdef wmb
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#define __io_bw() wmb()
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#else
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#define __io_bw() barrier()
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#endif
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#endif
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/* serialize device access against a spin_unlock, usually handled there. */
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#ifndef __io_aw
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#define __io_aw() barrier()
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#endif
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#ifndef __io_pbw
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#define __io_pbw() __io_bw()
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#endif
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#ifndef __io_paw
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#define __io_paw() __io_aw()
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#endif
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#ifndef __io_pbr
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#define __io_pbr() __io_br()
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#endif
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#ifndef __io_par
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#define __io_par() __io_ar()
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#endif
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/*
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* __raw_{read,write}{b,w,l,q}() access memory in native endianness.
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*
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@ -110,7 +154,12 @@ static inline void __raw_writeq(u64 value, volatile void __iomem *addr)
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#define readb readb
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static inline u8 readb(const volatile void __iomem *addr)
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{
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return __raw_readb(addr);
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u8 val;
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__io_br();
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val = __raw_readb(addr);
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__io_ar();
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return val;
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}
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#endif
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@ -118,7 +167,12 @@ static inline u8 readb(const volatile void __iomem *addr)
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#define readw readw
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static inline u16 readw(const volatile void __iomem *addr)
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{
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return __le16_to_cpu(__raw_readw(addr));
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u16 val;
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__io_br();
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val = __le16_to_cpu(__raw_readw(addr));
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__io_ar();
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return val;
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}
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#endif
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@ -126,7 +180,12 @@ static inline u16 readw(const volatile void __iomem *addr)
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#define readl readl
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static inline u32 readl(const volatile void __iomem *addr)
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{
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return __le32_to_cpu(__raw_readl(addr));
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u32 val;
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__io_br();
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val = __le32_to_cpu(__raw_readl(addr));
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__io_ar();
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return val;
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}
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#endif
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@ -135,7 +194,12 @@ static inline u32 readl(const volatile void __iomem *addr)
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#define readq readq
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static inline u64 readq(const volatile void __iomem *addr)
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{
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return __le64_to_cpu(__raw_readq(addr));
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u64 val;
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__io_br();
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val = __le64_to_cpu(__raw_readq(addr));
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__io_ar();
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return val;
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}
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#endif
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#endif /* CONFIG_64BIT */
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@ -144,7 +208,9 @@ static inline u64 readq(const volatile void __iomem *addr)
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#define writeb writeb
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static inline void writeb(u8 value, volatile void __iomem *addr)
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{
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__io_bw();
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__raw_writeb(value, addr);
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__io_aw();
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}
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#endif
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@ -152,7 +218,9 @@ static inline void writeb(u8 value, volatile void __iomem *addr)
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#define writew writew
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static inline void writew(u16 value, volatile void __iomem *addr)
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{
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__io_bw();
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__raw_writew(cpu_to_le16(value), addr);
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__io_aw();
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}
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#endif
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@ -160,7 +228,9 @@ static inline void writew(u16 value, volatile void __iomem *addr)
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#define writel writel
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static inline void writel(u32 value, volatile void __iomem *addr)
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{
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__io_bw();
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__raw_writel(__cpu_to_le32(value), addr);
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__io_aw();
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}
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#endif
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@ -169,7 +239,9 @@ static inline void writel(u32 value, volatile void __iomem *addr)
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#define writeq writeq
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static inline void writeq(u64 value, volatile void __iomem *addr)
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{
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__io_bw();
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__raw_writeq(__cpu_to_le64(value), addr);
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__io_aw();
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}
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#endif
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#endif /* CONFIG_64BIT */
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@ -180,35 +252,67 @@ static inline void writeq(u64 value, volatile void __iomem *addr)
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* accesses.
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*/
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#ifndef readb_relaxed
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#define readb_relaxed readb
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#define readb_relaxed readb_relaxed
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static inline u8 readb_relaxed(const volatile void __iomem *addr)
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{
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return __raw_readb(addr);
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}
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#endif
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#ifndef readw_relaxed
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#define readw_relaxed readw
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#define readw_relaxed readw_relaxed
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static inline u16 readw_relaxed(const volatile void __iomem *addr)
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{
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return __le16_to_cpu(__raw_readw(addr));
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}
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#endif
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#ifndef readl_relaxed
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#define readl_relaxed readl
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#define readl_relaxed readl_relaxed
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static inline u32 readl_relaxed(const volatile void __iomem *addr)
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{
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return __le32_to_cpu(__raw_readl(addr));
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}
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#endif
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#if defined(readq) && !defined(readq_relaxed)
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#define readq_relaxed readq
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#define readq_relaxed readq_relaxed
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static inline u64 readq_relaxed(const volatile void __iomem *addr)
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{
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return __le64_to_cpu(__raw_readq(addr));
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}
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#endif
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#ifndef writeb_relaxed
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#define writeb_relaxed writeb
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#define writeb_relaxed writeb_relaxed
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static inline void writeb_relaxed(u8 value, volatile void __iomem *addr)
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{
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__raw_writeb(value, addr);
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}
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#endif
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#ifndef writew_relaxed
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#define writew_relaxed writew
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#define writew_relaxed writew_relaxed
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static inline void writew_relaxed(u16 value, volatile void __iomem *addr)
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{
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__raw_writew(cpu_to_le16(value), addr);
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}
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#endif
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#ifndef writel_relaxed
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#define writel_relaxed writel
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#define writel_relaxed writel_relaxed
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static inline void writel_relaxed(u32 value, volatile void __iomem *addr)
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{
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__raw_writel(__cpu_to_le32(value), addr);
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}
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#endif
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#if defined(writeq) && !defined(writeq_relaxed)
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#define writeq_relaxed writeq
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#define writeq_relaxed writeq_relaxed
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static inline void writeq_relaxed(u64 value, volatile void __iomem *addr)
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{
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__raw_writeq(__cpu_to_le64(value), addr);
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}
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#endif
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/*
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@ -363,7 +467,12 @@ static inline void writesq(volatile void __iomem *addr, const void *buffer,
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#define inb inb
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static inline u8 inb(unsigned long addr)
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{
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return readb(PCI_IOBASE + addr);
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u8 val;
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__io_pbr();
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val = __raw_readb(PCI_IOBASE + addr);
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__io_par();
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return val;
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}
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#endif
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@ -371,7 +480,12 @@ static inline u8 inb(unsigned long addr)
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#define inw inw
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static inline u16 inw(unsigned long addr)
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{
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return readw(PCI_IOBASE + addr);
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u16 val;
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__io_pbr();
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val = __le16_to_cpu(__raw_readw(PCI_IOBASE + addr));
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__io_par();
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return val;
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}
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#endif
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@ -379,7 +493,12 @@ static inline u16 inw(unsigned long addr)
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#define inl inl
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static inline u32 inl(unsigned long addr)
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{
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return readl(PCI_IOBASE + addr);
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u32 val;
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__io_pbr();
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val = __le32_to_cpu(__raw_readl(PCI_IOBASE + addr));
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__io_par();
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return val;
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}
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#endif
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@ -387,7 +506,9 @@ static inline u32 inl(unsigned long addr)
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#define outb outb
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static inline void outb(u8 value, unsigned long addr)
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{
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writeb(value, PCI_IOBASE + addr);
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__io_pbw();
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__raw_writeb(value, PCI_IOBASE + addr);
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__io_paw();
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}
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#endif
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@ -395,7 +516,9 @@ static inline void outb(u8 value, unsigned long addr)
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#define outw outw
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static inline void outw(u16 value, unsigned long addr)
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{
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writew(value, PCI_IOBASE + addr);
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__io_pbw();
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__raw_writew(cpu_to_le16(value), PCI_IOBASE + addr);
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__io_paw();
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}
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#endif
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@ -403,7 +526,9 @@ static inline void outw(u16 value, unsigned long addr)
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#define outl outl
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static inline void outl(u32 value, unsigned long addr)
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{
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writel(value, PCI_IOBASE + addr);
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__io_pbw();
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__raw_writel(cpu_to_le32(value), PCI_IOBASE + addr);
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__io_paw();
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}
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#endif
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@ -1 +0,0 @@
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../../../arch/cris/boot/dts
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@ -1 +0,0 @@
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../../../arch/metag/boot/dts
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