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MLK-23131-1 arm64: dts: imx8mm/imx8mn: Add dram_pll_div clock for busfreq 

On i.MX8MM/i.MX8MN platforms, need to add dram_pll_div clock for
busfreq driver to update dram_core clock when DRAM frequency switches
between low bus mode and high bus mode.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Anson Huang 2019-12-19 14:29:53 +08:00
parent 4241039b94
commit c19e15747f
2 changed files with 6 additions and 4 deletions
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5
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -392,11 +392,12 @@
<&clk IMX8MM_SYS_PLL1_40M>, <&clk IMX8MM_SYS_PLL1_100M>,
<&clk IMX8MM_SYS_PLL2_333M>, <&clk IMX8MM_CLK_NOC>,
<&clk IMX8MM_CLK_AHB>, <&clk IMX8MM_CLK_MAIN_AXI>,
<&clk IMX8MM_CLK_24M>, <&clk IMX8MM_SYS_PLL1_800M>;
<&clk IMX8MM_CLK_24M>, <&clk IMX8MM_SYS_PLL1_800M>,
<&clk IMX8MM_DRAM_PLL>;
clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div",
"dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m",
"sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m",
"sys_pll1_800m";
"sys_pll1_800m", "dram_pll_div";
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
interrupt-name = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3";

5
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@ -204,11 +204,12 @@
<&clk IMX8MN_SYS_PLL1_40M>, <&clk IMX8MN_SYS_PLL1_100M>,
<&clk IMX8MN_SYS_PLL2_333M>, <&clk IMX8MN_CLK_NOC>,
<&clk IMX8MN_CLK_AHB>, <&clk IMX8MN_CLK_MAIN_AXI>,
<&clk IMX8MN_CLK_24M>, <&clk IMX8MN_SYS_PLL1_800M>;
<&clk IMX8MN_CLK_24M>, <&clk IMX8MN_SYS_PLL1_800M>,
<&clk IMX8MN_DRAM_PLL>;
clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div",
"dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m",
"sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m",
"sys_pll1_800m";
"sys_pll1_800m", "dram_pll_div";
};
power-domains {