drm/i915/ehl: Ungate DDIC and DDID
Specification states that DDI_CLK_SEL needs to be mapped to MG clock even if MG do not exist on EHL, this will ungate those DDIs. BSpec: 20845 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Vivek Kasireddy <vivek.kasireddy@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Tested-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190730175121.16413-1-jose.souza@intel.com
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@ -2921,6 +2921,12 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
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if (!intel_phy_is_combo(dev_priv, phy))
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if (!intel_phy_is_combo(dev_priv, phy))
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I915_WRITE(DDI_CLK_SEL(port),
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I915_WRITE(DDI_CLK_SEL(port),
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icl_pll_to_ddi_clk_sel(encoder, crtc_state));
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icl_pll_to_ddi_clk_sel(encoder, crtc_state));
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else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
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/*
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* MG does not exist but the programming is required
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* to ungate DDIC and DDID
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*/
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I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
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} else if (IS_CANNONLAKE(dev_priv)) {
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} else if (IS_CANNONLAKE(dev_priv)) {
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/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
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/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
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val = I915_READ(DPCLKA_CFGCR0);
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val = I915_READ(DPCLKA_CFGCR0);
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@ -2961,7 +2967,8 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
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enum phy phy = intel_port_to_phy(dev_priv, port);
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enum phy phy = intel_port_to_phy(dev_priv, port);
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if (INTEL_GEN(dev_priv) >= 11) {
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if (INTEL_GEN(dev_priv) >= 11) {
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if (!intel_phy_is_combo(dev_priv, phy))
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if (!intel_phy_is_combo(dev_priv, phy) ||
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(IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
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I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
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I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
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} else if (IS_CANNONLAKE(dev_priv)) {
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} else if (IS_CANNONLAKE(dev_priv)) {
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I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
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I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
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