dmaengine: driver for the iop32x, iop33x, and iop13xx raid engines
The Intel(R) IOP series of i/o processors integrate an Xscale core with raid acceleration engines. The capabilities per platform are: iop219: (2) copy engines iop321: (2) copy engines (1) xor and block fill engine iop33x: (2) copy and crc32c engines (1) xor, xor zero sum, pq, pq zero sum, and block fill engine iop34x (iop13xx): (2) copy, crc32c, xor, xor zero sum, and block fill engines (1) copy, crc32c, xor, xor zero sum, pq, pq zero sum, and block fill engine The driver supports the features of the async_tx api: * asynchronous notification of operation completion * implicit (interupt triggered) handling of inter-channel transaction dependencies The driver adapts to the platform it is running by two methods. 1/ #include <asm/arch/adma.h> which defines the hardware specific iop_chan_* and iop_desc_* routines as a series of static inline functions 2/ The private platform data attached to the platform_device defines the capabilities of the channels 20070626: Callbacks are run in a tasklet. Given the recent discussion on LKML about killing tasklets in favor of workqueues I did a quick conversion of the driver. Raid5 resync performance dropped from 50MB/s to 30MB/s, so the tasklet implementation remains until a generic softirq interface is available. Changelog: * fixed a slot allocation bug in do_iop13xx_adma_xor that caused too few slots to be requested eventually leading to data corruption * enabled the slot allocation routine to attempt to free slots before returning -ENOMEM * switched the cleanup routine to solely use the software chain and the status register to determine if a descriptor is complete. This is necessary to support other IOP engines that do not have status writeback capability * make the driver iop generic * modified the allocation routines to understand allocating a group of slots for a single operation * added a null xor initialization operation for the xor only channel on iop3xx * support xor operations on buffers larger than the hardware maximum * split the do_* routines into separate prep, src/dest set, submit stages * added async_tx support (dependent operations initiation at cleanup time) * simplified group handling * added interrupt support (callbacks via tasklets) * brought the pending depth inline with ioat (i.e. 4 descriptors) * drop dma mapping methods, suggested by Chris Leech * don't use inline in C files, Adrian Bunk * remove static tasklet declarations * make iop_adma_alloc_slots easier to read and remove chances for a corrupted descriptor chain * fix locking bug in iop_adma_alloc_chan_resources, Benjamin Herrenschmidt * convert capabilities over to dma_cap_mask_t * fixup sparse warnings * add descriptor flush before iop_chan_enable * checkpatch.pl fixes * gpl v2 only correction * move set_src, set_dest, submit to async_tx methods * move group_list and phys to async_tx Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Dan Williams <dan.j.williams@intel.com>hifive-unleashed-5.1
Dan Williams
parent
f6dff381af
commit
c211092313
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@ -31,4 +31,13 @@ config INTEL_IOATDMA
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default m
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---help---
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Enable support for the Intel(R) I/OAT DMA engine.
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config INTEL_IOP_ADMA
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tristate "Intel IOP ADMA support"
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depends on DMA_ENGINE && (ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX)
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select ASYNC_CORE
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default m
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---help---
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Enable support for the Intel(R) IOP Series RAID engines.
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endmenu
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@ -1,3 +1,4 @@
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obj-$(CONFIG_DMA_ENGINE) += dmaengine.o
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obj-$(CONFIG_NET_DMA) += iovlock.o
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obj-$(CONFIG_INTEL_IOATDMA) += ioatdma.o
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obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,118 @@
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/*
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* Copyright © 2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#ifndef IOP_ADMA_H
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#define IOP_ADMA_H
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#include <linux/types.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#define IOP_ADMA_SLOT_SIZE 32
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#define IOP_ADMA_THRESHOLD 4
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/**
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* struct iop_adma_device - internal representation of an ADMA device
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* @pdev: Platform device
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* @id: HW ADMA Device selector
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* @dma_desc_pool: base of DMA descriptor region (DMA address)
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* @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
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* @common: embedded struct dma_device
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*/
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struct iop_adma_device {
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struct platform_device *pdev;
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int id;
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dma_addr_t dma_desc_pool;
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void *dma_desc_pool_virt;
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struct dma_device common;
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};
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/**
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* struct iop_adma_chan - internal representation of an ADMA device
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* @pending: allows batching of hardware operations
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* @completed_cookie: identifier for the most recently completed operation
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* @lock: serializes enqueue/dequeue operations to the slot pool
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* @mmr_base: memory mapped register base
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* @chain: device chain view of the descriptors
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* @device: parent device
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* @common: common dmaengine channel object members
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* @last_used: place holder for allocation to continue from where it left off
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* @all_slots: complete domain of slots usable by the channel
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* @cleanup_watchdog: workaround missed interrupts on iop3xx
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* @slots_allocated: records the actual size of the descriptor slot pool
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* @irq_tasklet: bottom half where iop_adma_slot_cleanup runs
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*/
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struct iop_adma_chan {
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int pending;
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dma_cookie_t completed_cookie;
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spinlock_t lock; /* protects the descriptor slot pool */
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void __iomem *mmr_base;
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struct list_head chain;
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struct iop_adma_device *device;
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struct dma_chan common;
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struct iop_adma_desc_slot *last_used;
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struct list_head all_slots;
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struct timer_list cleanup_watchdog;
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int slots_allocated;
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struct tasklet_struct irq_tasklet;
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};
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/**
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* struct iop_adma_desc_slot - IOP-ADMA software descriptor
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* @slot_node: node on the iop_adma_chan.all_slots list
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* @chain_node: node on the op_adma_chan.chain list
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* @hw_desc: virtual address of the hardware descriptor chain
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* @phys: hardware address of the hardware descriptor chain
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* @group_head: first operation in a transaction
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* @slot_cnt: total slots used in an transaction (group of operations)
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* @slots_per_op: number of slots per operation
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* @idx: pool index
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* @unmap_src_cnt: number of xor sources
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* @unmap_len: transaction bytecount
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* @async_tx: support for the async_tx api
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* @group_list: list of slots that make up a multi-descriptor transaction
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* for example transfer lengths larger than the supported hw max
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* @xor_check_result: result of zero sum
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* @crc32_result: result crc calculation
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*/
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struct iop_adma_desc_slot {
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struct list_head slot_node;
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struct list_head chain_node;
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void *hw_desc;
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struct iop_adma_desc_slot *group_head;
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u16 slot_cnt;
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u16 slots_per_op;
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u16 idx;
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u16 unmap_src_cnt;
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size_t unmap_len;
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struct dma_async_tx_descriptor async_tx;
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union {
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u32 *xor_check_result;
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u32 *crc32_result;
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};
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};
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struct iop_adma_platform_data {
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int hw_id;
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dma_cap_mask_t cap_mask;
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size_t pool_size;
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};
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#define to_iop_sw_desc(addr_hw_desc) \
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container_of(addr_hw_desc, struct iop_adma_desc_slot, hw_desc)
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#define iop_hw_desc_slot_idx(hw_desc, idx) \
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( (void *) (((unsigned long) hw_desc) + ((idx) << 5)) )
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#endif
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