spi: dw: move to SPI core message handling
This patch removes a lot of duplicate code since SPI core provides a nice message handling. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>hifive-unleashed-5.1
Andy Shevchenko
Mark Brown
parent
3e00803a97
commit
c22c62db3f
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@ -110,7 +110,7 @@ static void dw_spi_dma_tx_done(void *arg)
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if (test_and_clear_bit(TX_BUSY, &dws->dma_chan_busy) & BIT(RX_BUSY))
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return;
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dw_spi_xfer_done(dws);
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spi_finalize_current_transfer(dws->master);
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}
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static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws)
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@ -155,7 +155,7 @@ static void dw_spi_dma_rx_done(void *arg)
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if (test_and_clear_bit(RX_BUSY, &dws->dma_chan_busy) & BIT(TX_BUSY))
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return;
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dw_spi_xfer_done(dws);
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spi_finalize_current_transfer(dws->master);
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}
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static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
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@ -28,11 +28,6 @@
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#include <linux/debugfs.h>
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#endif
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#define START_STATE ((void *)0)
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#define RUNNING_STATE ((void *)1)
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#define DONE_STATE ((void *)2)
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#define ERROR_STATE ((void *)-1)
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/* Slave spi_dev related */
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struct chip_data {
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u16 cr0;
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@ -143,6 +138,19 @@ static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
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}
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#endif /* CONFIG_DEBUG_FS */
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static void dw_spi_set_cs(struct spi_device *spi, bool enable)
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{
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struct dw_spi *dws = spi_master_get_devdata(spi->master);
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struct chip_data *chip = spi_get_ctldata(spi);
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/* Chip select logic is inverted from spi_set_cs() */
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if (chip->cs_control)
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chip->cs_control(!enable);
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if (!enable)
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dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
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}
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/* Return the max entries we can fill into tx fifo */
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static inline u32 tx_max(struct dw_spi *dws)
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{
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@ -209,93 +217,41 @@ static void dw_reader(struct dw_spi *dws)
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}
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}
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static void *next_transfer(struct dw_spi *dws)
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{
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struct spi_message *msg = dws->cur_msg;
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struct spi_transfer *trans = dws->cur_transfer;
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/* Move to next transfer */
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if (trans->transfer_list.next != &msg->transfers) {
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dws->cur_transfer =
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list_entry(trans->transfer_list.next,
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struct spi_transfer,
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transfer_list);
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return RUNNING_STATE;
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}
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return DONE_STATE;
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}
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/*
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* Note: first step is the protocol driver prepares
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* a dma-capable memory, and this func just need translate
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* the virt addr to physical
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*/
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static int map_dma_buffers(struct dw_spi *dws)
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static int map_dma_buffers(struct spi_master *master,
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struct spi_device *spi, struct spi_transfer *transfer)
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{
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if (!dws->cur_msg->is_dma_mapped
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struct dw_spi *dws = spi_master_get_devdata(master);
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struct chip_data *chip = spi_get_ctldata(spi);
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if (!master->cur_msg->is_dma_mapped
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|| !dws->dma_inited
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|| !dws->cur_chip->enable_dma
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|| !chip->enable_dma
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|| !dws->dma_ops)
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return 0;
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if (dws->cur_transfer->tx_dma)
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dws->tx_dma = dws->cur_transfer->tx_dma;
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if (transfer->tx_dma)
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dws->tx_dma = transfer->tx_dma;
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if (dws->cur_transfer->rx_dma)
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dws->rx_dma = dws->cur_transfer->rx_dma;
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if (transfer->rx_dma)
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dws->rx_dma = transfer->rx_dma;
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return 1;
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}
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/* Caller already set message->status; dma and pio irqs are blocked */
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static void giveback(struct dw_spi *dws)
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{
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struct spi_transfer *last_transfer;
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struct spi_message *msg;
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msg = dws->cur_msg;
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dws->cur_msg = NULL;
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dws->cur_transfer = NULL;
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dws->prev_chip = dws->cur_chip;
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dws->cur_chip = NULL;
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dws->dma_mapped = 0;
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last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
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transfer_list);
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if (!last_transfer->cs_change)
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spi_chip_sel(dws, msg->spi, 0);
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spi_finalize_current_message(dws->master);
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}
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static void int_error_stop(struct dw_spi *dws, const char *msg)
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{
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spi_reset_chip(dws);
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dev_err(&dws->master->dev, "%s\n", msg);
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dws->cur_msg->state = ERROR_STATE;
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tasklet_schedule(&dws->pump_transfers);
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dws->master->cur_msg->status = -EIO;
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spi_finalize_current_transfer(dws->master);
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}
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void dw_spi_xfer_done(struct dw_spi *dws)
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{
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/* Update total byte transferred return count actual bytes read */
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dws->cur_msg->actual_length += dws->len;
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/* Move to next transfer */
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dws->cur_msg->state = next_transfer(dws);
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/* Handle end of message */
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if (dws->cur_msg->state == DONE_STATE) {
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dws->cur_msg->status = 0;
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giveback(dws);
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} else
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tasklet_schedule(&dws->pump_transfers);
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}
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EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
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static irqreturn_t interrupt_transfer(struct dw_spi *dws)
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{
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u16 irq_status = dw_readw(dws, DW_SPI_ISR);
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@ -312,7 +268,7 @@ static irqreturn_t interrupt_transfer(struct dw_spi *dws)
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dw_reader(dws);
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if (dws->rx_end == dws->rx) {
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spi_mask_intr(dws, SPI_INT_TXEI);
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dw_spi_xfer_done(dws);
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spi_finalize_current_transfer(dws->master);
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return IRQ_HANDLED;
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}
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if (irq_status & SPI_INT_TXEI) {
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@ -327,13 +283,14 @@ static irqreturn_t interrupt_transfer(struct dw_spi *dws)
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static irqreturn_t dw_spi_irq(int irq, void *dev_id)
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{
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struct dw_spi *dws = dev_id;
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struct spi_master *master = dev_id;
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struct dw_spi *dws = spi_master_get_devdata(master);
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u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f;
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if (!irq_status)
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return IRQ_NONE;
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if (!dws->cur_msg) {
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if (!master->cur_msg) {
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spi_mask_intr(dws, SPI_INT_TXEI);
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return IRQ_HANDLED;
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}
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@ -342,7 +299,7 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id)
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}
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/* Must be called inside pump_transfers() */
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static void poll_transfer(struct dw_spi *dws)
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static int poll_transfer(struct dw_spi *dws)
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{
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do {
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dw_writer(dws);
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@ -350,17 +307,14 @@ static void poll_transfer(struct dw_spi *dws)
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cpu_relax();
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} while (dws->rx_end > dws->rx);
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dw_spi_xfer_done(dws);
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return 0;
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}
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static void pump_transfers(unsigned long data)
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static int dw_spi_transfer_one(struct spi_master *master,
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struct spi_device *spi, struct spi_transfer *transfer)
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{
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struct dw_spi *dws = (struct dw_spi *)data;
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struct spi_message *message = NULL;
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struct spi_transfer *transfer = NULL;
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struct spi_transfer *previous = NULL;
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struct spi_device *spi = NULL;
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struct chip_data *chip = NULL;
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struct dw_spi *dws = spi_master_get_devdata(master);
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struct chip_data *chip = spi_get_ctldata(spi);
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u8 bits = 0;
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u8 imask = 0;
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u8 cs_change = 0;
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@ -369,35 +323,8 @@ static void pump_transfers(unsigned long data)
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u32 speed = 0;
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u32 cr0 = 0;
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/* Get current state information */
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message = dws->cur_msg;
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transfer = dws->cur_transfer;
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chip = dws->cur_chip;
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spi = message->spi;
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if (message->state == ERROR_STATE) {
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message->status = -EIO;
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goto early_exit;
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}
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/* Handle end of message */
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if (message->state == DONE_STATE) {
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message->status = 0;
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goto early_exit;
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}
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/* Delay if requested at end of transfer */
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if (message->state == RUNNING_STATE) {
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previous = list_entry(transfer->transfer_list.prev,
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struct spi_transfer,
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transfer_list);
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if (previous->delay_usecs)
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udelay(previous->delay_usecs);
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}
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dws->n_bytes = chip->n_bytes;
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dws->dma_width = chip->dma_width;
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dws->cs_control = chip->cs_control;
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dws->rx_dma = transfer->rx_dma;
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dws->tx_dma = transfer->tx_dma;
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@ -405,7 +332,7 @@ static void pump_transfers(unsigned long data)
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dws->tx_end = dws->tx + transfer->len;
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dws->rx = transfer->rx_buf;
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dws->rx_end = dws->rx + transfer->len;
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dws->len = dws->cur_transfer->len;
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dws->len = transfer->len;
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if (chip != dws->prev_chip)
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cs_change = 1;
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@ -437,13 +364,12 @@ static void pump_transfers(unsigned long data)
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| (spi->mode << SPI_MODE_OFFSET)
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| (chip->tmode << SPI_TMOD_OFFSET);
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}
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message->state = RUNNING_STATE;
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/*
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* Adjust transfer mode if necessary. Requires platform dependent
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* chipselect mechanism.
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*/
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if (dws->cs_control) {
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if (chip->cs_control) {
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if (dws->rx && dws->tx)
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chip->tmode = SPI_TMOD_TR;
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else if (dws->rx)
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@ -456,10 +382,9 @@ static void pump_transfers(unsigned long data)
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}
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dw_writew(dws, DW_SPI_CTRL0, cr0);
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spi_chip_sel(dws, spi, 1);
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/* Check if current transfer is a DMA transaction */
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dws->dma_mapped = map_dma_buffers(dws);
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dws->dma_mapped = map_dma_buffers(master, spi, transfer);
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/* For poll mode just disable all interrupts */
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spi_mask_intr(dws, 0xff);
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@ -489,31 +414,17 @@ static void pump_transfers(unsigned long data)
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dws->dma_ops->dma_transfer(dws, cs_change);
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if (chip->poll_mode)
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poll_transfer(dws);
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return poll_transfer(dws);
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return;
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early_exit:
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giveback(dws);
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return 1;
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}
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static int dw_spi_transfer_one_message(struct spi_master *master,
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static void dw_spi_handle_err(struct spi_master *master,
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struct spi_message *msg)
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{
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struct dw_spi *dws = spi_master_get_devdata(master);
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dws->cur_msg = msg;
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/* Initial message state */
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dws->cur_msg->state = START_STATE;
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dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
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struct spi_transfer,
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transfer_list);
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dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
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/* Launch transfers */
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tasklet_schedule(&dws->pump_transfers);
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return 0;
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spi_reset_chip(dws);
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}
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/* This may be called twice for each spi dev */
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@ -637,7 +548,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
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snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
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ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
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dws->name, dws);
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dws->name, master);
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if (ret < 0) {
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dev_err(&master->dev, "can not get IRQ\n");
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goto err_free_master;
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@ -649,7 +560,9 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
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master->num_chipselect = dws->num_cs;
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master->setup = dw_spi_setup;
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master->cleanup = dw_spi_cleanup;
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master->transfer_one_message = dw_spi_transfer_one_message;
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master->set_cs = dw_spi_set_cs;
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master->transfer_one = dw_spi_transfer_one;
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master->handle_err = dw_spi_handle_err;
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master->max_speed_hz = dws->max_freq;
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master->dev.of_node = dev->of_node;
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@ -664,8 +577,6 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
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}
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}
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tasklet_init(&dws->pump_transfers, pump_transfers, (unsigned long)dws);
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spi_master_set_devdata(master, dws);
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ret = devm_spi_register_master(dev, master);
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if (ret) {
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@ -96,7 +96,6 @@ struct dw_spi_dma_ops {
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struct dw_spi {
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struct spi_master *master;
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struct spi_device *cur_dev;
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enum dw_ssi_type type;
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char name[16];
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@ -109,13 +108,7 @@ struct dw_spi {
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u16 bus_num;
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u16 num_cs; /* supported slave numbers */
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/* Message Transfer pump */
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struct tasklet_struct pump_transfers;
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/* Current message transfer state info */
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struct spi_message *cur_msg;
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struct spi_transfer *cur_transfer;
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struct chip_data *cur_chip;
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struct chip_data *prev_chip;
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size_t len;
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void *tx;
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@ -128,10 +121,8 @@ struct dw_spi {
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size_t rx_map_len;
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size_t tx_map_len;
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u8 n_bytes; /* current is a 1/2 bytes op */
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u8 max_bits_per_word; /* maxim is 16b */
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u32 dma_width;
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irqreturn_t (*transfer_handler)(struct dw_spi *dws);
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void (*cs_control)(u32 command);
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/* Dma info */
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int dma_inited;
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@ -182,22 +173,6 @@ static inline void spi_set_clk(struct dw_spi *dws, u16 div)
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dw_writel(dws, DW_SPI_BAUDR, div);
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}
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static inline void spi_chip_sel(struct dw_spi *dws, struct spi_device *spi,
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int active)
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{
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u16 cs = spi->chip_select;
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int gpio_val = active ? (spi->mode & SPI_CS_HIGH) :
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!(spi->mode & SPI_CS_HIGH);
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if (dws->cs_control)
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dws->cs_control(active);
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if (gpio_is_valid(spi->cs_gpio))
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gpio_set_value(spi->cs_gpio, gpio_val);
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if (active)
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dw_writel(dws, DW_SPI_SER, 1 << cs);
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}
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/* Disable IRQ bits */
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static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
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{
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@ -245,7 +220,6 @@ extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
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extern void dw_spi_remove_host(struct dw_spi *dws);
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extern int dw_spi_suspend_host(struct dw_spi *dws);
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extern int dw_spi_resume_host(struct dw_spi *dws);
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extern void dw_spi_xfer_done(struct dw_spi *dws);
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/* platform related setup */
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extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
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